This application discloses a data forwarding method and device. The method includes: obtaining a first data unit sequence stream by using a first logical ingress port, where the first data unit sequence stream includes at least one first data unit; determining, according to a preconfigured mapping relationship between at least one logical ingress port and at least one logical egress port, a first logical egress port corresponding to the first logical ingress port, where the at least one logical ingress port includes the first logical ingress port; adjusting a quantity of idle units in the first data unit sequence stream, so that a rate of an adjusted first data unit sequence stream matches a rate of the first logical egress port; and sending the adjusted first data unit sequence stream by using the first logical egress port.

A radio transmitter includes a data source, and write stream circuitry coupled to the data source. When a write stream mode is enabled and when there is valid write stream data available from the data source, the write stream circuitry is configured to transmit one or more write stream data symbols to a receiver. When there is no valid write stream data available from the data source, one or more idle symbols are transmitted to the receiver. Each of the idle symbols is randomly selected from a set of at least two idle symbols.

A radio transmitter includes a data source, and write stream circuitry coupled to the data source. When a write stream mode is enabled and when there is valid write stream data available from the data source, the write stream circuitry is configured to transmit one or more write stream data symbols to a receiver. When there is no valid write stream data available from the data source, one or more idle symbols are transmitted to the receiver. Each of the idle symbols is randomly selected from a set of at least two idle symbols.

A transmission device includes: a reception circuit; and a transmission section that is disposed between the reception circuit and a transmission circuit and transmits a clock signal and data signals in parallel, wherein the transmission circuit performs operations of: inserting a predetermined pattern in a data invalid period of each of the data signals; outputting the each of the data signals in which the predetermined pattern has been inserted in synchronization with an input clock; and adjusting a phase of the clock signal in the data invalid period, the reception circuit performs operations of: detecting a state of a reception clock using the data signals in which the predetermined pattern has been inserted; and determining whether phase adjustment of the clock signal is to be performed, based on the state of the reception clock, and the transmission circuit adjusts the phase of the clock signal, based on a determination result.

A transmission device includes: a reception circuit; and a transmission section that is disposed between the reception circuit and a transmission circuit and transmits a clock signal and data signals in parallel, wherein the transmission circuit performs operations of: inserting a predetermined pattern in a data invalid period of each of the data signals; outputting the each of the data signals in which the predetermined pattern has been inserted in synchronization with an input clock; and adjusting a phase of the clock signal in the data invalid period, the reception circuit performs operations of: detecting a state of a reception clock using the data signals in which the predetermined pattern has been inserted; and determining whether phase adjustment of the clock signal is to be performed, based on the state of the reception clock, and the transmission circuit adjusts the phase of the clock signal, based on a determination result.

A data transmitting device includes: a judge code generating portion for transmitting a plurality of times a predefined code pattern indicating a head portion of transmission data, as a judge code; a start code generating portion for transmitting at least once a start code having a predefined code pattern different from the judge code, following the judge code; and a valid data generating portion for transmitting valid data, following the start code. After receiving the judge code for a predetermined number of times that is less by at least one than the number of times that the judge code is transmitted, a data receiving device enters a standby state for receiving the start code, and, after receiving the start code, receives the valid data.

The present disclosure proposes a method for sending a cell stream, an apparatus for sending a cell stream, a network device, and a computer-readable storage medium. The method includes: detecting a time deviation value between an actual time of sending a cell in a designated device and a reference time; calculating a total number of code blocks corresponding to the time deviation value; and controlling the designated device to insert code blocks of a preset type into the cell stream to be sent according to the calculated number of code blocks, so as to adjust the actual time of sending the cell in the designated device to the reference time.

A serial transmission peripheral device for transmitting serial transmission data with a variable data length includes a pulse forming unit; and a register programmable to set a desired transmission length. The peripheral device is operable to determine an actual transmission length and calculate a length of a pause pulse and to add the pause pulse at the end of a transmission to generate a transmission having a constant length.

Technologies for robust data transmission include a network port logic having a physical coding sublayer (PCS). The PCS may transmit a series of rapid alignment markers (RAMs) to a link partner, with each RAM indicative of a counter value. The PCS transitions to a sleep state if the counter value equals two and a low power idle (LPI) command is set by an upper-layer client. The PCS transitions to an active state if the counter value equals one and the LPI command is not set. The PCS may receive a low power idle symbol (LI) from the link partner and start a guard timer in response to receipt of the LI symbol. The PCS transitions to a sleep state if the guard timer expires and transitions to the active state if data other than LI is received prior to expiration of the guard timer. Other embodiments are described and claimed.

An apparatus comprises a 64b66b encoder configured to process operations, administration, and maintenance (OAM) information, determine a bit pattern based on the OAM information, form forward error correction (FEC) parity sync-headers based on the bit pattern, and form an FEC codeword with the FEC parity sync-headers, and a transmitter coupled to the 64b66b encoder and configured to transmit the FEC codeword. A method comprises processing OAM information, determining a bit pattern based on the OAM information, forming FEC parity sync-headers based on the bit pattern, forming an FEC codeword with the FEC parity sync-headers, and transmitting the FEC codeword. An apparatus comprises a receiver configured to receive an FEC codeword, and a 64b66b decoder coupled to the receiver and configured to extract FEC parity sync-headers from the FEC codeword, determine a bit pattern of the FEC parity sync-headers, and determine OAM information based on the bit pattern.