A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.

A receiver is provided that includes a time-to-digital converter for converting a phase difference between a clock signal and a received data signal into a phase-difference digital code. The receiver also includes a logic circuit that controls a programmable delay line to delay the clock signal into a delayed clock signal by a delay that is responsive to a difference between the phase-difference code and a unit interval for the clock signal. The delayed clock signal clocks a flip-flop to register the received data signal.

In a communication system for performing serial communication between a transmitting device and a receiving device, the transmitting device transmits, to the receiving device, a first data signal including at least information on a transmission clock in one frame, and transmits, to the receiving device, a second data signal including at least information on the transmission clock in one frame, during a time period from transmission of the first data signal until transmission of the first data signal in the next transmission cycle. The receiving device receives the first data signal and the second data signal transmitted from the transmitting device.

A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.

A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

A preamble detection system and method includes converting the phase domain input samples corresponding to the preamble into frequency domain input samples. An I/Q-formatted dot product is generated from a dot product process between the frequency domain input samples and a reference pattern indicative of an expected preamble. The I/Q-formatted dot product is averaged with at least one previously generated I/Q-formatted dot product to generate an I/Q-formatted averaged dot product. The I/Q-formatted averaged dot product is converted into a polar-formatted averaged dot product, wherein the polar-formatted averaged dot product includes a magnitude of the polar-formatted averaged dot product and an angle of the polar-formatted averaged dot product. A preamble-found signal is then generated in response to the magnitude of the polar-formatted averaged dot product exceeding a preamble magnitude threshold.

An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.

The invention provides a method, device, storage medium and terminal device for controlling device operation, the method including: receiving a control signal sent by the control device, where the data structure of the control signal comprises a preamble, a header and a data packet in sequence, the preamble comprises an operating frequency, and the data packet comprises a control command; reading information from the control signal according to an arrangement timing of the control signal; when the preamble is read, adjusting an operating frequency of the receiving device according to the operating frequency included the preamble; when the header is read, the data packet is sampled according to a set sampling duration; and the sampled control command is executed according to the adjusted operating frequency. With the present invention, the control quality of the control signal is improved.