An Ethernet transceiver is disclosed. The Ethernet transceiver includes transceiver circuitry to couple to one end of an Ethernet link. The transceiver circuitry includes transmit circuitry to transmit high-speed Ethernet data along the Ethernet link at a first data rate and receiver circuitry. The receiver circuitry includes adaptive filter circuitry and correlator circuitry. The receiver circuitry is responsive to an inline signal to operate in a low-power alert mode with the adaptive filter circuitry disabled and to receive alert signals from the Ethernet link simultaneous with transmission of the Ethernet data by the transmit circuitry. The alert signals are detected by the correlator circuitry and include a sequence of alert intervals exhibiting encoded data at a second data rate less than the first data rate.

The disclosure provides a data communication method and apparatus, an electronic device, and a storage medium. The method includes: receiving controller area network (CAN) bus data transmitted by a first device; executing a first flow-control based transmission between the first connector and the first device to obtain respective consecutive frame data in multi-packet data from the first device, upon detecting that the CAN bus data is first frame data in the multi-packet data; and transmitting the first frame data and the respective consecutive frame data to a second connector to indicate that the second connector transmits the multi-packet data to a second device through a second flow-control based transmission, when or after executing the first flow-control based transmission between the first connector and the first device.

Methods, apparatus, systems, and articles of manufacture are disclosed to buffer an input voltage. An example apparatus includes first inverter circuitry to invert the input voltage and produce a first inverted voltage; second inverter circuitry coupled to the first inverter circuitry, the second inverter circuitry to invert the first inverted voltage and produce a second inverted voltage at a rate based on a first current controlled transistor; third inverter circuitry coupled to the second inverter circuitry, the third inverter circuitry to invert the second inverted voltage and produce a third inverted voltage at a rate based on a second current controlled transistor; and fourth inverter circuitry coupled to the third inverter circuitry, the fourth inverter circuitry to invert the third inverted voltage and produce an output voltage, wherein the output voltage matches the input voltage.

An overlap detection unit for a user station of a serial bus system. The overlap detection unit includes a collision detection block for detecting bus states on a bus of the bus system, in which, in order to transmit a message, bus states of user stations of the bus system are generated on the bus with a first physical layer in a first communication phase, and are generated with a second physical layer in a second communication phase, the second physical layer being different from the first physical layer. The collision detection block generates a signal whose value indicates whether or not the bus states in the second communication phase have a level that corresponds to an overlap of the first and second physical layers or an overlap of two second physical layers, and the collision detection block is designed to output the signal for the user station.

A 10GBASE-T circuit is disclosed. The circuit includes a physical (PHY) integrated circuit and a media access control (MAC) integrated circuit. The PHY couples to a data transfer medium and carries out data transfers at a PHY data rate. The MAC integrated circuit controls access to the date transfer medium and couples to the PHY via a bidirectional link operating at a MAC data rate. Rate control logic detects the PHY data rate, and adjusts the MAC data rate to the PHY data rate. Changes to the PHY and MAC data rates may be made at rates higher than 1 Gbps.

In an example, there is disclosed an apparatus, having: a first network interface, having a first clock and a local communication driver to communicatively couple the first network interface to a second network interface having a second clock; and one or more logic elements, including at least one hardware logic element, providing a synchronization engine to: send a first plurality of data words from the first wireless interface to the second wireless interface via the local communication driver; receive back from the second wireless interface a second plurality of data words; assign a plurality of error rates to the data words of the second plurality of data words, the plurality of error rates indicating match or mismatch; identify a range of least error values within the plurality of error rates; and select an agreed baud rate from within the range.

Described is a digital interface and related systems, method and devices. In some embodiments, an interface may be an interface between a link layer and a physical transmission medium. The interface may be configured for a bit rate and/or reference clock that limits electromagnetic emissions (EME), for example, as compared to a bit rate and/or clock rate specified by interfaces widely used in industry.

A physical-layer circuit including a memory, a physical-layer device and a control circuit. The memory receives data from a media access controller (MAC) at a first rate. The MAC is separate from the physical-layer circuit. The physical-layer device receives the data from the memory and transmits the data from the physical-layer circuit to a peer device. The physical-layer device transfers the data from the memory to the peer device at a second rate. An amount of data stored in the memory is based on a difference between the first and second rates. The second rate is less than the first rate. The control circuit is connected between the memory and the physical layer device. The control circuit monitors the amount of the data stored in the memory and, based on the amount of the data stored in the memory, transmits a frame to the MAC to decrease the first rate.

In a method for serial communication of data frames between nodes connected by a bus system, the transmitter and receiver roles are assigned to the nodes for each data frame by the arbitration procedure defined in the CAN-Standard ISO 11898-1. The exchanged data frames, which include multiple bits, have a logical structure according to the CAN-Standard ISO 11898-1, including a Start-Of-Frame-Bit, an Arbitration Field, a Control Field, a Data Field, a CRC Field, an Acknowledge Field and an End-Of-Frame Field. Each bit has a bit time which is divided into Time Segments. In response to a predefined value of a specific bit within the Control Field a first node of a first node group restarts its protocol decoding state machine and waits until it has synchronized itself to the bus activity and a second node of a second node group communicates using CAN FD Specification protocol.

A method for exchanging data between nodes which are connected to each other by a bus system, in which messages that contain data are exchanged according to a first communication protocol; the messages are made up of a sequence of bits; at least one control bit having a predetermined position within the message, which is exchanged according to the first protocol, must have a predetermined value; for each message, one node has the role of transmitter and at least one other node, as receiver, receives the message and monitors the message for errors, wherein by transmission of the control bit having a value differing from the predetermined value, at least one first receiver is transferred into a protocol exception state, so that it suspends error monitoring, and the transmitter, after transmitting the control bit, begins to transmit further data according to a second protocol to at least one second receiver.