Methods and systems for hardware-accelerated packet multicasting are provided. According to one embodiment, a first multicast packet to be multicast to a first multicast destination is received by a virtual routing system. The multicast packet is caused to be transmitted to the multicast destination by: (i) directing the multicast packet to a first VR of multiple VRs instantiated within the virtual routing system by selecting the first VR from among the multiple VRs to multicast the multicast packet; (ii) configuring the virtual routing system to use a routing context associated with the selected VR in connection with processing of the multicast packet; (iii) reading at least a portion of the multicast packet from one of multiple multicast address spaces associated with the selected VR; and (iv) forwarding the multicast packet to the first multicast destination. Similar steps are then performed for a second multicast packet.

A method for estimation of a network path segment delay includes determining a scaled time stamp for each packet of a plurality of packets by scaling a time stamp for each respective packet to minimize a difference of at least one of a frequency and a frequency drift between a transport protocol clock of a host and a monitoring point. The time stamp for each packet is provided by the transport protocol clock of the host. A corrected time stamp for each packet is determined by removing from the scaled time stamp for each respective packet, a temporal offset between the transport protocol clock and the monitoring clock by minimizing a temporal delay variation of the plurality of packets traversing a segment between the host and the monitoring point.

Provided are a method and apparatus for implementing scheduling in a Ping process. An MAC layer of an eNB learns about the traffic of UE, determines whether the UE is carrying out Ping according to a learning result, determines a period of sending a data packet by the UE when determining that the UE is carrying out Ping and carries out pre-scheduling according to the period. According to the technology of implementing scheduling in the Ping process in the present disclosure, a high layer can report the traffic statistic to the MAC layer; and the MAC layer learns continuously based on a set learning period so as to judge whether the UE is carrying out Ping, and determines the period of sending a data packet by the UE when determining that the UE is carrying out Ping to predict the coming of a next data packet for the Ping and carry out pre-scheduling, thereby saving the time of sending an SR by the UE; in this way, the time delay for the Ping is considered, moreover, the technology can be used in the network all the time and do not affect the traffic of a system.

A system for adaptive audio video (AV) stream processing may include at least one processor and a switch device. The switch device may be configured to route AV traffic to the processor, and to receive AV traffic from the processor and provide the AV traffic to a client device via one or more channels. The processor may monitor a transcoder buffer depth and depths of buffers associated with channels over which the AV traffic is being transmitted. The processor may adaptively modify one or more attributes associated with the AV traffic based at least on the monitored buffer depths. For example, the processor may adaptively adjust a bit rate associated with transcoding the AV traffic based at least on the transcoder buffer depth. The processor may utilize the depths of the buffers associated with the channels to adaptively adjust the amount of AV traffic provided for transmission over the channels.

A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.

The invention includes, among other things, a system for passing TDM traffic through a packet switch. In one embodiment, the system includes a packet switch that has a plurality of data ports and is capable of routing FSDU packets between the plurality of data ports. A TDM encapsulation circuit process a TDM data flow that is incoming to the switch. A circuit demultiplexer processes the incoming data flow to buffer data associated with different TDM circuits into different buffer locations. A timer monitors the amount of time available to fill the FSDU, and when the time period reaches the frame boundary, an FSDU generator generates an FSDU that is filled with data associated with the TDM circuits. Header information is added for allowing the packet switch to route the generated FSDU to a port associated with the respective TDM circuit.

A multi-channel decoder circuit associated with a multi-channel decoder system is disclosed. The multi-channel decoder circuit comprises a distributed decoder circuit comprising a set of unit decoder circuits, each unit decoder circuit configured to receive one or more codewords of a plurality of codewords associated with a plurality of input channels, and decode the one or more codewords. The multi-channel decoder circuit further comprises a distribution controller circuit configured to distribute each incoming codeword of the one or more codewords to the respective unit decoder circuit of the set of unit decoder circuits within the distributed decoder circuit, based on determining a currently available unit decoder circuit within the set of unit decoder circuits.