The description that follows relates to a circuit having galvanic isolation. According to an exemplary embodiment, the circuit has a transmission circuit, coupled to a galvanically isolating device, that is designed to transmit a first signal via the galvanically isolating device. The circuit further has a first receiver circuit, coupled to the galvanically isolating device, that is designed to receive the transmitted first signal from the galvanically isolating device. A second receiver circuit coupled to the galvanically isolating device is designed to receive the transmitted first signal from the galvanically isolating device and to take the received first signal as a basis for generating a wake-up signal.

A low voltage drive circuit (LVDC) includes a digital to digital converter that converts transmit digital data into a digital input signal, wherein the transmit digital data is synchronized to a clock rate of a host device and the digital input signal is synchronized to a clock rate of a bus to which the LVDC is coupled. An output limited digital to analog is converter converts the digital input signal into analog outbound data by generating a DC component and converting the digital input signal into an oscillating component at a first frequency, wherein magnitude of the oscillating component is limited to a range that is less than a difference between magnitudes of power supply rails of the LVDS, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit conveys the analog outbound data as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

An oscillator for use in pulse communication of pulse signals with a startup latency and a pulse oscillation signal (such as for use in a transmitter for OOK pulse communication with pulse modulation). The oscillator includes an LC resonator having a tank impedance, and including a high-side node (Vp), and a low-side node Vn, and having a tank voltage corresponding to [Vp-Vn]. A pulse startup circuit, includes a PMOS transistor with a source connected to a supply voltage VDD, and a drain connected through a resistance R to the Vp node (where R is significantly larger than the tank impedance), and connected to an attenuation capacitance, in parallel with the resistance R. The PMOS control terminal is coupled to receive a kick start pulse to initiate a pulse signal. the oscillator can include high-side and low-side pulse startup circuits.

A signal isolator integrated circuit package includes a first circuit having a first input and a first output, a second circuit having a second input and a second output, an isolation barrier layer between the first circuit and the second circuit, wherein the second output of the second circuit is coupled to the first input of the first circuit through the isolation barrier. The signal isolator includes a comparator configured to compare the first input of the first circuit to the second output of the second circuit. The second output can be configured to convey at least three states, including a first state indicative of a logical high of an input signal received at the first input, a second state indicative of a logical low of the input signal, and a third state indicative of a fault condition.

Implementations provide a receiver circuit that includes: an alternate current (AC)-coupling network to filter an input signal, the AC-coupling network including a first RC filter connected between a first input node and a first common node and a second RC filter connected between a second input node and the first common node; a differential amplifier coupled to the AC-coupling network and configured to receive a filtered input signal from the AC-coupling network and generate an output signal, the differential amplifier including a differential pair of transistors and a common-mode measurement network coupled to source terminals of a first and a second transistors in the differential pair; and a first operational amplifier having an input coupled to output terminal of the common-mode measurement network and an output coupled to the first common node.

According to one embodiment, a digital isolator includes a first metal portion, a first insulating portion, a second metal portion, a third metal portion, and a first layer. The first insulating portion is provided on the first metal portion. The second metal portion is provided on the first insulating portion. The third metal portion includes first, second, and third portions. The first portion is provided around the first metal portion in a direction perpendicular to a first direction. The second portion is provided on a portion of the first portion with a first conductive layer interposed. The third portion is provided on the second portion and provided around the second metal portion in the perpendicular direction. The first layer contacts the first conductive layer and an other portion of the first portion and is provided around a bottom portion of the second portion.

Circuitry to automatically compensate a differential output oscillator circuit for common mode disturbances that may affect the oscillator output. For any differential oscillator the common mode voltage excursion may reduce the oscillator output, which in some examples may negatively affect the circuitry receiving the oscillator output. The addition of feedback circuitry with an automatic gain control, e.g., to regulate the differential output voltage, may further reduce the gain of the oscillator in the presence of common mode voltage. In contrast, the feedback circuitry of the oscillator circuit of this disclosure may include gain control circuitry to increase an output voltage amplitude at the differential output terminals for a duration of the common mode disturbance.

An isolation circuit that isolates a driver circuit that is biased at a first common mode voltage from a detection circuit that is biased at a second common mode voltage using isolation capacitors. The detection circuit includes a transimpedance amplifier having improved susceptibility to transient common-mode input signals and improved insensitivity to parasitic capacitance on the isolation capacitor terminals. Included within the transimpedance amplifier are circuits for mirroring current to convert the input current from the isolation capacitors into a voltage value and to amplify that voltage value. The transimpedance amplifier outputs a differential voltage value that is held by a latch circuit so that a comparator in the detection circuit can process the differential voltage value and output a differential signal with fully restored logic levels.

A PoDL system that uses a center-tapped transformer, for galvanic isolation of the PHY, has AC-coupling capacitors in series between the transmission wires and the transformer's secondary windings for blocking DC voltages generated by a PSE power supply. The center tap is conventionally connected to ground. As a result, one capacitor sees the full VPSE voltage across it, and the other capacitor sees approximately 0V across it. Since the effective value of a ceramic capacitor significantly reduces with increasing DC bias voltages across it, the effective values of the capacitors will be very different, resulting in unbalanced data paths. This can lead to conversion of common mode noise and corrupt the data. To avoid this, a resistor divider is used to generate VPSE/2, and this voltage is applied to the center tap of the transformer. Therefore, the DC voltage across each capacitor is approximately VPSE/2, so their values remain equal.

Systems for power over data line applications with low mode conversion are described. For example, an apparatus may include a magnetic core; a first conductive coil wound in a first winding direction around the magnetic core; a second conductive coil wound in a second winding direction around the magnetic core; a first conductive lead connecting a first end of the first conductive coil to a first pin; a second conductive lead connecting a second end of the first conductive coil to a second pin; a third conductive lead connecting a first end of the second conductive coil to a third pin, wherein lengths of the first conductive lead and the third conductive lead are equal; and a fourth conductive lead connecting a second end of the second conductive coil to a fourth pin, wherein lengths of the second conductive lead and the fourth conductive lead are equal.