Data isolators for providing isolation between two ports that enable dynamic communication are described. The dynamic communication may be achieved by varying a ratio of the data rate relative to a clock frequency of a clock signal. The data isolator may include a first circuit that transmits data across an isolation barrier when the clock signal is in a first state and a second circuit that transmits data across the isolation barrier when the clock signal is in a second state. The clock frequency may be variable and, as a result, change the duration of data transmissions in a given clock cycle. For example, the clock frequency may be reduced to increase the number of bits transmitted per clock cycle and, conversely, increased to reduce the number of bits transmitted per clock cycle. Thus, the number of bits transmitted per clock cycle may be adjusted to suit the situation.

A PoDL system conducts differential data and DC power over the same wire pair, and various DC coupling techniques are described that improve DC voltage coupling while attenuating AC common mode noise. Pairs of differential mode chokes (DMCs) are used to share current supplied by a power supply. In one embodiment, one DMC is coupled to the line side of a common mode choke (CMC), and one DMC is coupled to the PHY side of the CMC. The line-side DMC has windings that are loosely magnetically coupled so that DMC does not present a very low impedance to AC common mode noise on the wires. Therefore, the performance of the wires' RC termination circuitry is not adversely affected by the line-side DMC when minimizing reflections of common mode signals. The DMCs may use the same magnetic core, and the CMC may be series CMCs that used the same magnetic core.

Data isolators for providing isolation between two ports that enable dynamic communication are described. The dynamic communication may be achieved by varying a ratio of the data rate relative to a clock frequency of a clock signal. The data isolator may include a first circuit that transmits data across an isolation barrier when the clock signal is in a first state and a second circuit that transmits data across the isolation barrier when the clock signal is in a second state. The clock frequency may be variable and, as a result, change the duration of data transmissions in a given clock cycle. For example, the clock frequency may be reduced to increase the number of bits transmitted per clock cycle and, conversely, increased to reduce the number of bits transmitted per clock cycle. Thus, the number of bits transmitted per clock cycle may be adjusted to suit the situation.

To improve the quality of transmission of a signal from an image sensor to a camera controller of an endoscopy arrangement by a cable while maintaining electrical safety standards, a first circuitry arrangement used to transmit the signal within the cable includes galvanic isolation from a second circuitry arrangement used to further process the signal within the camera controller. The galvanic isolation is formed downstream of a proximal end of the cable in the signal direction, and the first circuitry arrangement has a, preferably passive, impedance matching circuit, for example arranged at the proximal end of the cable or in the camera controller. This impedance matching circuit is configured to compensate signal distortions, which arise during the transmission of the signal that is produced by the image sensor to the camera controller, preferably such that a frequency spectrum of the signal produced by the image sensor can be reproduced.

A system comprising a rack and at least one line replaceable module, the rack further comprising a primary transmission circuit comprising a primary antenna, primary emission components designed to generate an emitted power containing uplink data, and primary receiving components designed to receive downlink data, the line replaceable module comprising a secondary transmission circuit comprising a secondary antenna, secondary receiving components designed to receive the emitted power and the uplink data, and secondary emission components designed to generate the downlink data, the emitted power, the uplink data and the downlink data being transmitted via a shared coupling between the primary antenna and the secondary antenna.

Provided is a semiconductor integrated circuit that improves insulation reliability between a high-voltage circuit and a low-voltage circuit. The semiconductor integrated circuit includes the following: a first circuit controlled by a control signal of low voltage and driven at a higher voltage; a second circuit configured to output the control signal to the first circuit to control the driving of the first circuit; and an insulation circuit including insulating elements connected to each other in series, the insulation circuit connecting between the first and the second circuits in series. The insulation circuit is configured to magnetically or capacitively couple the control signal in each insulating element to transmit the control signal from the second circuit to the first circuit, and is configured to insulate the first circuit from the second circuit in each insulating element to prevent the higher voltage from being applied between the first and second circuits.

A transmission device according to the disclosure includes: a controller that selects one of a plurality of operation modes; and a first transmitter that includes a first capacitance setting section that sets a load capacitance in accordance with an operation mode selected by the controller, and is configured to be able to output, to a first output terminal, a first signal having a signal format according to the selected operation mode, among a plurality of signal formats.

Various examples are directed to a rotary coupler and methods of use thereof. The rotary data coupler may comprise a transmitter and receiver. The transmitter may comprise a first band and a second transmitter band. The receiver may comprise a receiver housing positioned to rotate relative to the first transmitter band and the second transmitter band. A first receiver band may be positioned opposite the first transmitter band to form a first capacitor and a second receiver band may be positioned opposite the second transmitter band to form a second capacitor. The receiver may also comprise a resistance electrically coupled between the first receiver band and the second receiver band and a differential amplifier. The differential amplifier may comprise an inverting input and a non-inverting input, with the non-inverting input electrically coupled to the first receiver band and the inverting input electrically coupled to the second receiver band.

Methods, systems, and apparatus to increase common-mode transient immunity in isolation devices is disclosed. An example apparatus includes a current mirror including an input terminal and an output terminal; a transistor including a gate terminal, a first current terminal, and a second current terminal, the gate terminal coupled to a reference voltage terminal, the first current terminal coupled to the input terminal of the current mirror, and the second current terminal coupled to an input node; a buffer including an input terminal and an output terminal, the input terminal of the buffer coupled to the output terminal of the current mirror; and a logic gate including an input terminal and an output terminal, the input terminal of the logic gate coupled to the output terminal of the buffer.

Methods, systems, and apparatus to increase common-mode transient immunity in isolation devices is disclosed. An example apparatus includes a current mirror including an input terminal and an output terminal; a transistor including a gate terminal, a first current terminal, and a second current terminal, the gate terminal coupled to a reference voltage terminal, the first current terminal coupled to the input terminal of the current mirror, and the second current terminal coupled to an input node; a buffer including an input terminal and an output terminal, the input terminal of the buffer coupled to the output terminal of the current mirror; and a logic gate including an input terminal and an output terminal, the input terminal of the logic gate coupled to the output terminal of the buffer.