A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.

A package structure for a capacitive coupling isolator is provided. The package structure includes a first and a second leadframes, a transmitter, a receiver and a packaging body. The first leadframe includes a first and a second signal input pins and a first electrode plate, and the second leadframe includes a first and a second signal output pins and a second electrode plate. The first and second electrode plates are arranged one above another and aligned with each other for forming a plurality of capacitors. The transmitter is disposed on the first leadframe and the receiver is disposed on the second leadframe. The packaging body encloses the first and second leadframes and is filled therebetween for electrically isolating the first and second leadframes from each other.

An EHF receiver that determines an initial slicing voltage level and dynamically adjusts the slicing voltage level and/or amplifier gain levels to account for characteristics of the received EHF electromagnetic data signal. The architecture includes an amplifier, detector, adaptive signal slicer, and controller. The detector includes a main detector and replica detector that convert the received EHF electromagnetic data signal into a baseband signal and a reference signal. The controller uses the baseband signal and reference signal to determine an initial slicing voltage level, and dynamically adjust the slicing voltage level and the gain settings of the amplifier to compensate for changing signal conditions.

Disclosed examples include digital isolator modules, isolation circuitry and low-loss multi-order bandpass filter circuits, including a capacitive coupled galvanic isolation circuit with first and second coupling capacitors individually including a first plate and a second plate, and a bond wire connecting the first plates of the coupling capacitors, a first circuit with a first inductor coupled to form a first resonant tank circuit with a first parasitic capacitor associated with the second plate of the first coupling capacitor, and a second circuit with a second inductor coupled to form a second resonant tank circuit with a second parasitic capacitor associated with the second plate of the second coupling capacitor.

Systems and methods are disclosed for improving common mode transient immunity in silicon digital isolators using capacitive barrier for galvanic isolation. The systems include transmitters and receivers that include differential amplifiers. The differential amplifier may include a first transistor electrically coupled between a first input of the transmitter and a first output of the transmitter, a second transistor electrically coupled between a second input of the transmitter and a second output of the transmitter, a first passive load electrically coupled between the first input of the transmitter and a source rail, and a second passive load electrically coupled between the second input of the transmitter and the source rail, wherein the first and second passive loads have the same impedance; and a bias voltage source configured to bias a gate of the first transistor and a gate of the second transistor.

A circuit includes an isolator that provides isolated signal communications between a host-side circuit and a converter-side circuit. The isolated signal communications include a conversion start signal generated in the host-side circuit passing through the isolator to become an isolated conversion start signal in the converter-side circuit. The isolated signal communications includes an isolated system clock generated in the converter-side circuit passing through the isolator to become a system clock in the host-side circuit. A sampling clock generator in the host-side circuit generates the conversion start signal based on the system clock. A logic circuit in the converter-side circuit re-clocks the isolated conversion start signal through the logic circuit.

According to one embodiment, an isolator includes a first electrode, a second electrode, a conductive body, and a first insulating layer. The second electrode is provided on the first electrode and separated from the first electrode. The conductive body is provided around the first and second electrodes along a first plane perpendicular to a first direction. The first direction is from the first electrode toward the second electrode. The first insulating layer is provided on the second electrode. The first insulating layer includes silicon, carbon, and nitrogen.

A communication barrier arrangement includes a first driver having a first interface for receiving signals from a first device destined for a second device, an isolation barrier including a first transformer for signal transfer and having a primary winding connected to the first driver and a secondary winding, a second driver connected to the secondary winding and having a first connection terminal for output of the signals towards the second device, a first signal conditioner having a second connection terminal for receiving the signals from the second driver and a second interface for delivering them to the second device and a protection circuit including a resistor in parallel with a first capacitor, the protection circuit being connected between the first and second connection terminals.

A signal transmission device is constituted by a transformer chip having, for example, a first wiring layer, a second wiring layer different from the first wiring layer, a primary winding formed in the first wiring layer, a secondary winding formed in the second wiring layer to be magnetically coupled with the primary winding, and a shield electrode formed to be interposed between the primary and secondary windings.

A digital isolator includes: an edge detection circuit configured to output a first detection signal and a second detection signal; a driving buffer circuit configured to output a first edge signal and a second edge signal; an isolation element configured to output a first edge signal and a second edge signal; a receiving inverter circuit configured to output a first reception signal and a second reception signal; a latch circuit configured to latch data based on the pulse of the first received signal and the pulse of the second received signal, and to output an output signal to an output terminal according to the data; a switch circuit configured to switch a state of conduction between the reference potential and the first output and a state of conduction between the reference potential and the second output; and a control circuit configured to control a switching operation.