The disclosed embodiments include multi-channel communications filters, multi-channel communications systems, apparatuses that utilize a tunable multi-channel communications filter for antenna tuning, and methods to perform multi-channel communications filter tuning. A multi-channel communications filter includes a coupled inductor having a primary winding that is coupled to a power source, and magnetically coupled to one or more secondary windings. The multi-channel communications filter also includes a tuning bank formed from a first set of capacitors; and a first set of switches that are configured to adjust capacitance of the first set of capacitors to impede signals having a first frequency range from flowing through the multi-channel communications filter. The tuning bank and the first set of switches are coupled to the one or more secondary windings.

An electronic device has a substrate and first and second metallization levels with a resonant circuit. The first metallization level has a first dielectric layer on a side of the substrate, and a first metal layer on the first dielectric layer. The second metallization level has a second dielectric layer on the first dielectric layer and the first metal layer, and a second metal layer on the second dielectric layer. The electronic device includes a first plate in the first metal layer, and a second plate spaced apart from the first plate in the second metal layer to form a capacitor. The electronic device includes a winding in one of the first or second metal layers and coupled to one of the first or second plates in a resonant circuit.

Methods, systems, and apparatus described herein make a multi-level PAM signal (PAM-N signal) at a transmitter using CMOS-based components. By forming the PAM-N signal at the transmitter, receivers do not have to recombine and/or realign multiple signals and only employs a single transmission line channel (or two transmission line channels in differential implementations) to convey the data stream to the receiver from the transmitter.

A bidirectional capacitive isolator includes a capacitive isolation network, a first transceiver circuit, and a second transceiver circuit. The capacitive isolation network includes a first port and a second port. The first transceiver circuit is coupled to the first port of the capacitive isolation network, and includes circuitry configured to cancel signal transmitted by the first transceiver circuit from signal received by the first transceiver circuit. The second transceiver circuit is coupled to the second port of the capacitive isolation network, and includes circuitry configured to cancel signal transmitted by the second transceiver circuit from signal received by the second transceiver circuit.

A capacitive coupling circuit device is provided with a capacitive coupling circuit and a ground-side feedback circuit. The capacitive coupling circuit demodulates a modulated signal, which is obtained by modulating an input signal and transmitting a modulated input signal through a coupling capacitor. The ground-side feedback circuit is inserted between a first ground terminal on a signal input side of the capacitive coupling circuit and a second ground terminal on a signal output side of the capacitive coupling circuit. The ground-side feedback circuit is configured by connecting a second capacitor in series to a parallel circuit of a first capacitor and a first resistor. Alternatively, the ground-side feedback circuit may be configured by connecting the second capacitor and a third capacitor in series to both ends of the parallel circuit of the first capacitor and the first resistor, respectively.

Methods and apparatus are disclosed for communicating multiple logic states across a digital isolator. The digital isolator is a universal serial bus (USB) isolator in some embodiments. The digital isolator includes one or more single-bit data channels. Three or more logic states of information are transmitted across the single-bit data channel(s). The logic states are distinguished by a pulse sequence, and in particular a number of edges of the pulse sequence and a final value or final edge of the pulse sequence.

An integrated circuit with galvanic isolation is described herein. In accordance with one example, the circuit comprises a galvanic insulation barrier including a first isolation element configured to separate a first isolation domain from a second isolation domain and a first channel configured to transmit—in a first mode of operation and across the first isolation element—a logic signal from a first input in the first isolation domain to a first output in the second isolation domain. The first channel is further configured to transmit—in a second mode of operation and across the first isolation element—a serial data stream from the first input to a logic circuit in the second isolation domain, wherein the logic circuit is configured to receive—in the second mode of operation—the serial data stream and to store configuration information included in the serial data stream in a memory.

A multi-voltage domain device includes a semiconductor layer including a first voltage domain, a second voltage domain, and an isolation region that electrically isolates the first voltage domain and the second voltage domain in a lateral direction. The isolation region includes at least one deep trench isolation barrier. A layer stack is arranged on the semiconductor layer and includes a stack insulator layer, a first coil arranged in the stack insulator layer, and a second coil arranged in the stack insulator layer and laterally separated from the first coil in the lateral direction. The first and second coils are magnetically coupled to each other in the lateral direction. The first coil includes terminals arranged vertically over the first region and are electrically coupled to the first voltage domain, and the second coil includes terminals arranged vertically over the second region and are electrically coupled to the second voltage domain.

Disclosed is a driver of an ethernet transmitter and a control method therefor. The driver has a first output port and a second output port connected to an ethernet receiver through a transmission line, and comprises: a signal conversion module for converting differential current signals into a first voltage signal and a second voltage signal; a first driving module adjusting a swing of the first voltage signal, to obtain a first output signal having a voltage equal to the first voltage signal; a second driving module adjusting a swing of the second voltage signal, to obtain a second output signal having a voltage equal to the second voltage signal. An architecture having a relatively small area is realized, and the ethernet transmitter meets the requirement on a large output swing in 10 BASE-T mode.

A differential communication driver circuit includes a drive unit that drives differential signal lines connected via capacitors by a source current and a sink current. When a noise detection unit detects that in-phase noise is applied to the differential signal lines, a drive assisting unit maintains an amplitude of a differential signal output to the differential signal lines by increasing a current drive capability of the sink current.