A parallel-serial conversion circuit including a data transmission unit to output first data and second data of a prescribed pattern in accordance with a second clock obtained by dividing a first clock, a first flip flop to receive the first data so as to output the first data in accordance with the first clock, a second flip flop to receive the second data so as to output the second data in accordance with the first clock, a selector to select one of the first data and the second data so as to output the selected data in accordance with the first clock, and an adjustment unit to compare the second data to be received by the second flip flop and the first data output from the first flip flop so as to adjust, based on a comparison result, a timing for the first flip flop to receive the first data.

An electronic device includes a signal sender that sends a pair of transmission signals of mutually opposite phases to an external device via a pair of transmission paths. The signal sender differentiates each amplitude of the pair of transmission signals.

Embodiments of a passive buffer circuit and a wideband communication circuit that uses the passive buffer circuit are disclosed. In an embodiment, the passive buffer circuit includes buffer elements connected between input terminals and output terminals that are connected to input terminals of a communication component circuit with a plurality of input transistors. Each of the buffer elements provides a first path with a resistor and a second path with a series-connected capacitor and inductor. The passive buffer circuit further includes current sources connected between the output terminals and at least one fixed voltage and a feedback loop from the input transistors to the current sources to control direct current (DC) voltage at each of the input terminals of the communication component circuit. The feedback loop includes an error amplifier that controls the current sources based on voltages on the input transistors with respect to a reference voltage.

Implementations described herein include surgical helmet assemblies that have a helmet enclosure shaped to encircle a head of a user. The helmet enclosure retains a fan and includes a brow bar portion at a front of the helmet enclosure that is shaped to extend along a brow or a forehead of the user and having a light positioned therein. The helmet enclosure also includes a stabilizer extending downward from the helmet enclosure in front of the ears of a user, a face shield that is transparent and coupleable to at least the brow bar portion, a headband shaped to extend across an occiput region of the user's head, and a surgical garment for covering at least the head and shoulders of a user in use. The brow bar portion includes vents disposed therein to direct airflow pushed through the helmet enclosure from the fan onto the user. The face shield is coupleable to the helmet enclosure by one or more of a hook and loop fastener on the helmet enclosure or the stabilizer and a post protruding from the brow bar portion.

Methods are described allowing a vector signaling code to encode multi-level data without the significant alphabet size increase known to cause symbol dynamic range compression and thus increased noise susceptibility. By intentionally restricting the number of codewords used, good pin efficiency may be maintained along with improved system signal-to-noise ratio.

An emission reduction device for a CAN bus system. The device includes an evaluation block for evaluating signals that are transferred differentially on two bus lines, the evaluation block being designed to form the sum voltage of the differentially transferred signals, and a comparison block for comparing the sum voltage in such a way that the difference between the sum voltage for a dominant bus state and the sum voltage for a recessive bus state has a predetermined minimum value, the recessive bus state being overwritable by a dominant bus state. For the comparison, the comparison block is designed to modify at least one property of the transceiver device via a setting in a block of the transceiver device until the difference between the sum voltage for a dominant bus state and the sum voltage for a recessive bus state has the predetermined minimum value.

System, methods and apparatus are described that facilitate communication of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A receiving device receives a sequence of symbols over a multi-wire link. The receiving device further receives a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link. The receiving device decodes the sequence of symbols using the clock signal. In an aspect, a second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols. Accordingly, the receiving device decodes the sequence of symbols using the clock signal received via the dedicated clock line while ignoring the second clock signal.

Described is an apparatus for boosting a transition edge of a signal, the apparatus comprises: a logic to provide input data having a Unit Interval (UI); a programmable delay unit to receive the input data and operable to delay the input data by a fraction of the UI to generate a delayed input data; and one or more drivers to drive the input data and the delayed input data to a node.

The disclosed embodiments relate to the design of an equalizer that uses both cross-coupled cascodes and inductive peaking to reduce distortion in a signal received from a communication channel by attenuating lower frequencies and amplifying higher frequencies. At lower frequencies, when the effects of inductive impedance within the equalizer are negligible, the equalizer essentially functions as a traditional cascode amplifier that presents high gain. At higher frequencies, the increases in inductive impedances within the equalizer act to boost a gain of the equalizer.

A termination for a high-frequency transmission line includes a first resistor that has a first terminal coupled to a first end of a transmission line and a second terminal coupled to a first input/output pad, and a second resistor that has a first terminal coupled to the first input/output pad. The first resistor and the second resistor may provide a combined resistance that matches a nominal value of a characteristic impedance of the transmission line. The apparatus may include a third resistor having a first terminal coupled to a second end of a transmission line, and a second terminal coupled to a second input/output pad, and a fourth resistor having a first terminal coupled to the second input/output pad. The third resistor and the fourth resistor may provide a combined resistance that matches the nominal value of the characteristic impedance of the transmission line.