A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.

Differential signal skew compensation techniques for radio frequency interference (RFI) mitigation with no reflection penalty and associated apparatus and methods. A differential pair of signal traces are formed on or in a PCB having at least two changes in direction, with a first signal trace having a first routing path defining a first length and a second signal trace adjacent to the first signal trace including one or more tuning structures that are configured such that the length of the second signal trace matches the first length. Segments of the first signal trace adjacent to the one or more tuning structures of the second signal trace are widened relative to other segments of the first signal trace. The tuning structures may comprise sawtooth structures, accordion structures and other serpentine or meander structures. The solution mitigates RFI without a reflection penalty.

The present disclosure relates to devices and methods for detecting and preventing occurrence of a saturation state in a power amplifier. A power amplifier module can include a power amplifier including a cascode transistor pair. The cascode transistor pair can include a first transistor and a second transistor. The power amplifier module can include a current comparator configured to compare a first base current of the first transistor and a second base current of the second transistor to obtain a comparison value. The power amplifier module can include a saturation controller configured to supply a reference signal to an impedance matching network based on the comparison value. The impedance matching network can be configured to modify a load impedance of a load line in electrical communication with the power amplifier based at least in part on the reference signal.

A semiconductor apparatus includes a calibration circuit, a selection circuit, and a data circuit. The calibration circuit generates a plurality of calibration signals by being coupled to a plurality of reference resistors. The selection circuit selects at least one signal among the plurality of calibration signals on the basis of an impedance setting signal. The data circuit sets an impedance based on the selected calibration signal.

A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.

The driver circuit includes a pull-up network having a first pull-up transistor controlled by a data signal, a second pull-up transistor coupled between the first pull-up transistor and a first power supply voltage, and a third pull-up transistor coupled in parallel with the second pull-up transistor. The third pull-up transistor is configured to turn on for at least one clock cycle responsive to a change in the logic level of the data signal being detected.

Disclosed is a driver of an ethernet transmitter and a control method therefor. The driver has a first output port and a second output port connected to an ethernet receiver through a transmission line, and comprises: a signal conversion module for converting differential current signals into a first voltage signal and a second voltage signal; a first driving module adjusting a swing of the first voltage signal, to obtain a first output signal having a voltage equal to the first voltage signal; a second driving module adjusting a swing of the second voltage signal, to obtain a second output signal having a voltage equal to the second voltage signal. An architecture having a relatively small area is realized, and the ethernet transmitter meets the requirement on a large output swing in 10 BASE-T mode.

Systems, methods, and processor readable media for distributing digital data and electrical power to a plurality of devices over high-impedance cables are disclosed. Certain embodiments include a gateway device connected to a power source, a first device connected to the gateway device by a cable, the cable being a high-impedance cable having at least two conductive paths, and wherein the first device receives electrical power and digital data from the gateway device via the cable over the same conductive path of the cable, a second device connected to the gateway device by the cable wherein the second device receives power and digital data from the gateway device via the cable over the same conductive path, and wherein the power source provides power to the first and second devices via the cable, and wherein the second device is connected to the gateway device through the first device via a daisy-chain topology.

A voltage-mode transmitter includes a calibration circuit having a replica circuit. By adjusting a feedback voltage driving a gate of a replica transistor in the replica circuit so that an impedance of the replica circuit matches an impedance of a variable resistor, the calibration circuit calibrates an output impedance of a single slice driver.

A memory controller and/or memory device control termination of a communication link in order to achieve power savings while reducing or eliminating unwanted reflections in the channel. Following transmission of data over the communication channel, termination is left enabled for a programmable time period beginning immediately following completion of the transmission. The time period is sufficiently long to allow the unwanted reflections to be absorbed by the termination. Following the time period, the termination is disabled for power savings.