A front-end module is provided. The front-end module includes a reception amplifier configured to amplify a received radio-frequency (RF) signal, first and second series switches configured to control a switching operation to electrically connect an output terminal of the reception amplifier and first and second reception ports to each other, a radio-frequency (RF) splitter configured to simultaneously transfer a received RF signal, amplified by the reception amplifier or bypassing the reception amplifier, to the first and second reception ports, first and second shunt switches configured to control a switching operation to electrically connect a ground and first and second branch nodes between the RF splitter and the first and second reception ports to each other, and first and second reflected wave removing impedance elements electrically connected between the first and second branch nodes and a ground.

A circuit is provide comprising a first input coupled to a transmit data input of a bus transceiver; and a first output coupled to a bus. The circuit is configured to be coupled in parallel with the bus transceiver. The circuit is further configured to, in response to a dominant to recessive transition on the transmit data input, lower an impedance of the bus.

A line driver circuit having an amplifier circuit having a differential output, the differential output including a first output terminal and a second output terminal and an impedance switching circuit coupled between the first output terminal and the second output terminal of the amplifier circuit, wherein the impedance switching circuit is configured to reduce or maintain impedance across the first output terminal and the second output terminal of the amplifier circuit.

A driver circuit for driving a transmission line includes a voltage driver and a current driver. The voltage driver is for driving the transmission line with a first voltage gain in a first operation mode. The current driver is activatable in a second operation mode for driving, together with the voltage driver, the transmission line with a second voltage gain. The transmission line may be an Ethernet-over-copper transmission line with electrical data signals from a data generator.

There is provided an interface circuit, a network switch or network device coupler incorporating the interface circuit, and a network incorporating the network switch or network device. The interface circuit has a data bus interface (7) for connecting a data bus to either a first device (6) that communicates in a first signalling protocol or a second device (6) that communicates in a second signalling protocol. The data bus has two bus conductors that provide combined power and data. A voltage source (12) powers the data bus. The voltage source (12) is connected to the data bus via a reactance (10) and then a first resistance (4) connected in series. An output of a transmitter (13) is connected via a second resistance (3) to a point between the reactance (10) and the first resistance, to modulate the data bus.

A circuit is provided for ringing suppression. The circuit comprises a termination resistor coupled to a bus via a switch; and a control circuit. The control circuit comprises an input coupled to a data input pin of a bus transceiver and an output coupled to control the termination resistor. The circuit is configured to selectively couple the resistor to the bus in response to a transition on the input bit stream.

An apparatus comprising a plurality of driver circuits and a plurality of control registers. The plurality of driver circuits may be configured to modify a memory signal that transfers read data across a read line to a memory controller. The plurality of control registers may be configured to enable one or more of the driver circuits. A pull up strength and a pull down strength of the memory signal may be configured in response to how many of the plurality of driver circuits are enabled. The plurality of driver circuits implement an asymmetric pull up and pull down of the memory signal.

A reflection attenuation device for a bus of a bus system and a method for attenuating reflections during a data transfer in a bus system. The reflection attenuation device may close off a free end of bus lines of the bus in a transceiver device of a user station of the bus system. Alternatively, the reflection attenuation device may be connected to a branch point of the bus which is a star point or is used to connect a user station to the bus. Thus, bus users in a vehicle trailer are also connectable to the bus system of the vehicle, as needed. The reflection attenuation device includes at least one pair of electrical semiconductor components connected in parallel, and at least one capacitor that is connected in series to the pair of electrical semiconductor components connected in parallel, for attenuating reflections on a bus line of the bus.

A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method including: transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and transmitting a command to the second memory device through the data signal line while the memory controller receives the first data, wherein a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line, and the first data and the command are transmitted in both directions of the data signal line.

Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor and a calibration circuit. The calibration circuit determines whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chip. The timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips.