Apparatus and associated methods relate to an I/O bank impedance calibration circuit having (a) a replica master resistor coupled to an external precision resistor, and (b) a control circuit configured to calibrate an output impedance of the master resistor to generate a calibrated code to control a replica slave resistor in each bank. In an illustrative example, a signal applied to the replica master resistor may be compared against a programmable reference signal. The control circuit may generate the calibrated code, in response to the comparison result, to calibrate the output impedance of the replica master resistor. By implementing the replica master resistor and the replica slave resistor, impedances of a large number of IOs or banks may be calibrated by the impedance calibration circuit using a single one reference pin.

A Controller Area Network, CAN, transceiver comprising: two terminals for coupling to a CAN bus; a transmitter arrangement configured to transmit signalling on the bus based on transmit data, the transmitter arrangement configured to drive the bus to a dominant state or recessive state based on the transmit signal; an impedance control device; a signalling detector to determine the length of time the transmit data comprises a logic zero prior to a transition to a logic one state and: based on the length of time being longer than a predetermined threshold, provide for control of an output impedance by the impedance control device in accordance with a first scheme; and based on the length of time being shorter than said predetermined threshold, provide for one of: control of said output impedance in accordance with a second scheme; and no control of the output impedance by the impedance control device.

A receiver includes a first T-coil circuit at an input of the receiver and configured to receive an input signal, a termination impedance coupled to the first T-coil circuit and configured to match an impedance of a transmission line coupled to the first T-coil circuit, and an amplifier including a first input and a second input and configured to amplify a differential signal at the first and second inputs, a calibration switch coupled to the amplifier and configured to selectively electrically connect or disconnect the first and second inputs of the amplifier, and a first receive switch configured to selectively electrically connect or disconnect a center node of the first T-coil circuit and the amplifier.

A transmission device according to the disclosure includes a driver section that is able to transmit a data signal by using three or more predetermined number of voltage states and set voltages in each of the voltage states; and a control section that sets an emphasis voltage that is based on a transition among the predetermined number of the voltage states, and thereby causes the driver section to perform emphasis.

A deskew circuit for a differential signal is provided. A first common mode voltage generating circuit generates a first common mode voltage signal according to first and second differential input signals. A voltage buffer circuit is coupled to the first common mode voltage generating circuit and has an input impedance higher than a preset value, and buffers the first common mode voltage signal and the first and second differential input signals to generate a second common mode voltage signal, a third differential input signal, and a fourth differential input signal. A second common mode voltage generating circuit is coupled to the voltage buffer circuit and generates a third common mode voltage signal according to the third and fourth differential input signals. An output circuit generates a deskew output signal according to the third and fourth differential input signals and the second and third common mode voltage signals.

In a transmission device connected by AC coupling, time taken before the start of transmission of valid data is shortened. The transmission device includes an internal resistor, an internal circuit, and a transmission-side control unit. One end of the internal resistor is connected to an output terminal connected to a capacitor. The internal circuit supplies one of a plurality of potentials different from each other to another end of the internal resistor. The transmission-side control unit performs control to supply one of the plurality of potentials to the internal circuit over a period from time when a potential of the output terminal is initialized to a predetermined initial value to timing when the potential of the output terminal reaches a predetermined specified value.

A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.

A system may include a transmitter, a receiver, a cable coupled between the transmitter and the receiver and having two wires for communicating a differential signal from the transmitter to the receiver, and a direct-current (DC) voltage source coupled to a first wire of the two wires of the cable and configured to apply a variable DC offset voltage to the first wire in order to vary an impedance of the cable as a function of the variable DC offset voltage.

A digital-to-analog converter (DAC)-based voltage-mode transmit driver architecture. One example transmit driver circuit generally includes an impedance control circuit coupled to a plurality of DAC driver slices. The impedance control circuit generally includes a tunable impedance configured to be adjusted to match a load impedance for the transmit driver circuit. Another example transmit driver circuit generally has an output impedance that is smaller than the load impedance for the transmit driver circuit, such that an output voltage swing at differential output nodes of the transmit driver circuit is greater than a voltage of a power supply rail. Another example transmit driver circuit generally includes a predriver circuit with a first inverter coupled to a first output of the predriver circuit and a second inverter coupled to a second output of the predriver circuit, the transistors in at least one of the first inverter or the second inverter having different strengths.

A Controller Area Network, CAN, transceiver comprising: two terminals for coupling to a CAN bus; a transmitter arrangement configured to transmit signalling on the bus based on transmit data, the transmitter arrangement configured to drive the bus to a dominant state or recessive state based on the transmit signal; an impedance control device; a signalling detector to determine the length of time the transmit data comprises a logic zero prior to a transition to a logic one state and: based on the length of time being longer than a predetermined threshold, provide for control of an output impedance by the impedance control device in accordance with a first scheme; and based on the length of time being shorter than said predetermined threshold, provide for one of: control of said output impedance in accordance with a second scheme; and no control of the output impedance by the impedance control device.