A reflection attenuation device for a bus of a bus system and a method for attenuating reflections during a data transfer in a bus system. The reflection attenuation device may close off a free end of bus lines of the bus in a transceiver device of a user station of the bus system. Alternatively, the reflection attenuation device may be connected to a branch point of the bus which is a star point or is used to connect a user station to the bus. Thus, bus users in a vehicle trailer are also connectable to the bus system of the vehicle, as needed. The reflection attenuation device includes at least one pair of electrical semiconductor components connected in parallel, and at least one capacitor that is connected in series to the pair of electrical semiconductor components connected in parallel, for attenuating reflections on a bus line of the bus.

A system and method for efficiently transporting data in a computing system are contemplated. In various embodiments, a computing system includes a source, a destination and multiple lanes between them for transporting data. Multiple receivers in the destination has a respective termination resistor connected to a single integrating capacitor, which provides a reference voltage to the multiple receivers. The receivers reconstruct the received data by comparing the corresponding input signals to the reference voltage. The source includes a table storing code words. The source maps a generated data word to a code word, which is sent to the destination. The destination maps the received code word to the data word. The values of the code words are selected to maintain a nearly same number of Boolean ones on the multiple lanes over time as a number of Boolean zeroes.

Apparatus might include a first plurality of signal lines, a second plurality of signal lines, a controller, a first die, and a second die. The controller, the first die, and the second die might each be connected to the first plurality of signal lines and connected to the second plurality of signal lines. The first die and the second die might each include termination circuitry connected to a particular signal line of the second plurality of signal lines. The first die might be configured to activate its termination circuitry in response to receiving a particular combination of signal values on the first plurality of signal lines. The second die might be configured to deactivate its termination circuitry in response to receiving the particular combination of signal values on the first plurality of signal lines.

Systems, methods, and processor readable media for distributing digital data and electrical power to a plurality of devices over high-impedance cables are disclosed. Certain embodiments include a gateway device connected to a power source, a first device connected to the gateway device by a cable, the cable being a high-impedance cable having at least two conductive paths, and wherein the first device receives electrical power and digital data from the gateway device via the cable over the same conductive path of the cable, a second device connected to the gateway device by the cable wherein the second device receives power and digital data from the gateway device via the cable over the same conductive path, and wherein the power source provides power to the first and second devices via the cable, and wherein the second device is connected to the gateway device through the first device via a daisy-chain topology.

Systems, methods, and processor readable media for distributing digital data and electrical power to a plurality of devices over high-impedance cables are disclosed. Certain embodiments include a gateway device connected to a power source, a first device connected to the gateway device by a cable, the cable being a high-impedance cable having at least two conductive paths, and wherein the first device receives electrical power and digital data from the gateway device via the cable over the same conductive path of the cable, a second device connected to the gateway device by the cable wherein the second device receives power and digital data from the gateway device via the cable over the same conductive path, and wherein the power source provides power to the first and second devices via the cable, and wherein the second device is connected to the gateway device through the first device via a daisy-chain topology.

The present disclosure relates to devices and methods for detecting and preventing occurrence of a saturation state in a power amplifier. A power amplifier module can include a power amplifier including a cascode transistor pair. The cascode transistor pair can include a first transistor and a second transistor. The power amplifier module can include a current comparator configured to compare a first base current of the first transistor and a second base current of the second transistor to obtain a comparison value. The power amplifier module can include a saturation controller configured to supply a reference signal to an impedance matching network based on the comparison value. The impedance matching network can be configured to modify a load impedance of a load line in electrical communication with the power amplifier based at least in part on the reference signal.

A differential communication circuit is connected to a communication line formed of a positive communication line and a negative communication line for differential communication. The differential communication circuit includes: a series circuit that includes a resistor element and a connection switch. The resistor element is connected between the positive and negative communication lines when the connection switch is turned on. The circuit also includes a transmission unit that is configured to output a differential signal to the communication line and a controller that is configured to change impedance of the communication line by turning on the connection switch in a period during which the transmission unit does not output the differential signal.

A transmission circuit includes a first terminal to which a first voltage is applied, a second terminal, a third terminal, and a fourth terminal to which a second voltage lower than the first voltage is applied. The transmission circuit further includes a first variable resistance circuit between the first and second terminals, a second variable resistance circuit between the third and fourth terminals, and a controller that controls the resistance values of the first and second variable resistance circuits based on transmission data. The first and second variable resistance circuits are each a parallel circuit of a plurality of series circuits of a resistor and a switch. The first and second variable resistance circuits each include a charge adjuster that absorbs and discharges electric charge with respect to at least some of a plurality of switches.

CAN bus drive slew rate control is used to suppress ringing using bus impedance matching that is only activated during and shortly after the bus driver unit transitions from driving the bus “dominant” to “recessive”. In one embodiment a bus impedance matching unit is a differential input and differential output operational trans-conductance amplifier (OTA). The differential OTA absorbs or provides the ringing current based on bus differential voltage. In another embodiment a bus impedance matching unit is a back-to-back connected R.sub.ON regulated transistor pair together with a gate control related circuit. Where the total R.sub.ON is equal to the CAN bus characteristic impedance.

A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.