Systems, methods, and processor readable media for distributing digital data and electrical power to a plurality of devices over high-impedance cables are disclosed. Certain embodiments include a gateway device connected to a power source, a first device connected to the gateway device by a cable, the cable being a high-impedance cable having at least two conductive paths, and wherein the first device receives electrical power and digital data from the gateway device via the cable over the same conductive path of the cable, a second device connected to the gateway device by the cable wherein the second device receives power and digital data from the gateway device via the cable over the same conductive path, and wherein the power source provides power to the first and second devices via the cable, and wherein the second device is connected to the gateway device through the first device via a daisy-chain topology.

Memory devices might include an input/output (I/O) node, a termination device, an array of memory cells in communication with the I/O node through the termination device, and control circuitry, wherein the control circuitry is configured to compare an address received by the memory device to a plurality of instances of address information stored in the memory device. Each instance of address information of the plurality of instances of address information might correspond to a respective termination value stored in the memory device. In response to the memory device receiving an address matching an instance of address information stored in the memory device, the control circuitry might further be configured to activate the termination device using the respective termination value corresponding to the instance of address information matching the received address.

Systems and techniques that facilitate smart CAN termination are provided. In various embodiments, a system can comprise a sensor component that can measure an impedance of a controller area network (CAN) bus. In various aspects, the system can further comprise a termination component that can convert at least one node of the CAN bus from a non-terminating state to a terminating state, based on the impedance.

A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.

A system may include a transmitter, a receiver, a cable coupled between the transmitter and the receiver and having two wires for communicating a differential signal from the transmitter to the receiver, and a direct-current (DC) voltage source coupled to a first wire of the two wires of the cable and configured to apply a variable DC offset voltage to the first wire in order to vary an impedance of the cable as a function of the variable DC offset voltage.

An active termination circuit comprising an input node connected to a transmission line, a first transistor, and a second transistor. The transmission line supplies a signal to the input node. The first transistor is diode connected between a high voltage supply and the input node. The first transistor terminates the signal when the signal is at a low logic level. The second transistor is diode connected between the input node and a low voltage supply. The second transistor terminates the signal when the signal is at a high logic level.

CAN bus drive slew rate control is used to suppress ringing using bus impedance matching that is only activated during and shortly after the bus driver unit transitions from driving the bus “dominant” to “recessive”. In one embodiment a bus impedance matching unit is a differential input and differential output operational trans-conductance amplifier (OTA). The differential OTA absorbs or provides the ringing current based on bus differential voltage. In another embodiment a bus impedance matching unit is a back-to-back connected R.sub.ON regulated transistor pair together with a gate control related circuit. Where the total R.sub.ON is equal to the CAN bus characteristic impedance.

A circuit for a transmitter driver is disclosed. The transmitter driver circuit includes a main voltage-mode driver circuit configured to receive an input signal at the input port and to drive an output signal at the output port. The transmitter driver circuit also includes a secondary circuit connected to the input port and the output port in parallel with the main voltage-mode driver circuit. The secondary circuit includes: a secondary voltage-mode driver circuit; a current source connected to the secondary voltage-mode driver circuit and controllable to enable or disable a current boost to the output signal; and a switch connected to the secondary voltage-mode driver circuit and controllable to enable or disable the secondary voltage-mode driver circuit to drive the output signal in parallel with the main voltage-driver circuit.

A line driver circuit has first and second differential input terminals and first and second differential output terminals, and is configured to interface with first and second termination impedances coupled between the first and second differential output terminals, respectively, and first and second transmit chain output terminals, respectively. The line driver circuit includes an amplifier circuit having first and second input terminals coupled to the first and second differential input terminals of the line driver circuit, respectively, and first and second output terminals coupled to the first and second differential output terminals of the line driver circuit, respectively, and an impedance switching circuit coupled between the first and second output terminals of the amplifier circuit. The impedance switching circuit switches between a first switching mode and a second switching mode, wherein in the first switching mode a first switching configuration is established resulting in a first output impedance.

Methods and systems are described for receiving a plurality of signals via a plurality of wires of a multi-wire bus, the plurality of signals corresponding to symbols of a codeword of a vector signaling code, generating, using an interconnected resistor network connected to the plurality of wires of the multi-wire bus, a plurality of combinations of the symbols of the codeword of the vector signaling code on a plurality of output nodes, the plurality of output nodes including a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels, and generating a plurality of sub-channel outputs using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes.