A Controller Area Network, CAN, transceiver comprising: two terminals for coupling to a CAN bus; a transmitter arrangement configured to transmit signalling on the bus based on transmit data, the transmitter arrangement configured to drive the bus to a dominant state or recessive state based on the transmit signal; an impedance control device; a signalling detector to determine the length of time the transmit data comprises a logic zero prior to a transition to a logic one state and: based on the length of time being longer than a predetermined threshold, provide for control of an output impedance by the impedance control device in accordance with a first scheme; and based on the length of time being shorter than said predetermined threshold, provide for one of: control of said output impedance in accordance with a second scheme; and no control of the output impedance by the impedance control device.

A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

A bus driving device includes at least three high-side output drivers and at least three low-side output drivers. A part of the high-side output drivers and a part of the low-side output drivers are alternately coupled in series, and the remains of the high-side output drivers and the low-side output drivers are alternately coupled in series. The part of the high-side output drivers and the part of the low-side output drivers receive an input digital signal and sequentially drive a first supply bus and a second supply bus based on the input digital signal, and the remains of the high-side output drivers and the low-side output drivers receive the inverted input digital signal and sequentially drive the first supply bus and the second supply bus based on the inverted input digital signal.

A signal receiver and a signal transceiver are provided, which may avoid unnecessary leakage current. The signal receiver includes a termination switch pair, a first resistor, a second resistor, and a pull-down circuit. The termination switch pair receives an operation power supply. The termination switch pair has a common control end. The first resistor is coupled between a first signal input end and the common control end. The second resistor is coupled between a second signal input end and the common control end. The pull-down circuit is coupled between the common control end and a reference voltage end. The pull-down circuit determines whether to pull down a first control voltage on the common control end to a reference voltage according to a power-on state or a power-off state of the signal receiver.

An equalizing transmitter coupled to a serial transmission line has a driver circuit coupled between an input signal and the serial transmission line, the driver circuit being configured to receive power at a first voltage level. The equalizing transmitter has one or more helper circuits, each helper circuit being configured to receive a control signal and to pull the serial transmission line to a second voltage level when a pulse is present in the control signal. The second voltage level may be greater than the first voltage level. The equalizing transmitter has one or more pulse generation circuits, each pulse generation circuit being configured to receive the input signal and a delayed version of the input signal and to provide the pulse in the control signal when a difference in voltage state is detected between the input signal and the delayed version of the input signal.

A Low Voltage Differential Signaling (LVDS) transmitter includes driver circuit with a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor. The first transistor is coupled between a first node and first output. The second transistor is coupled between the first node and a second output. The third transistor is coupled between the first output and a second node. The fourth transistor is coupled between the second output and the second node. The first resistor is coupled between the first output and a common mode node. The second resistor is coupled between the second output and the common mode node. A pre-driver circuit generates gate control signals controlling the first, second, third, and fourth transistors in response to a data signal. A controlled timing delay is applied to the timing of logic state transistors for the control signals.

A user station for a bus system and a method for transmitting a message at different bit rates in a bus system. The user station includes a transmitting stage for transmitting a message on a bus line of the bus system. The transmitting stage switches between a first operating mode and a second operating mode when transmitting different phases of a message. The transmitting stage, in the first operating mode, generates a first data state as a bus state having different bus levels for two bus wires of the bus line, and generates a second data state as a bus state having the same bus level for the two bus wires of the bus line. The transmitting stage, in the second operating mode, generates the first and second data state in each case as a bus state having different bus levels for the two bus wires of the bus line.

An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.

In a transmission device connected by AC coupling, time taken before the start of transmission of valid data is shortened. The transmission device includes an internal resistor, an internal circuit, and a transmission-side control unit. One end of the internal resistor is connected to an output terminal connected to a capacitor. The internal circuit supplies one of a plurality of potentials different from each other to another end of the internal resistor. The transmission-side control unit performs control to supply one of the plurality of potentials to the internal circuit over a period from time when a potential of the output terminal is initialized to a predetermined initial value to timing when the potential of the output terminal reaches a predetermined specified value.

Provided is a method and an apparatus for optimizing memory power and provide a method and an apparatus for optimizing memory power by minimizing power consumed by pins of a memory by using an SBR pattern. The method of optimizing memory power using a PAM-4 (Pulse-Amplitude Modulation-4) method includes: setting a ratio and sizes of a pull-up transistor and a pull-down transistor included in a driver according to a smallest size of a plurality of eyes included in an eye diagram of a memory; and setting a reference voltage of a sampler and a phase interpolator (PI) digital code value included in the memory by using a signal bit response (SBR) pattern.