A transmission device of the present disclosure includes: a driver unit that transmits a data signal with use of a first voltage state, a second voltage state, and a third voltage state interposed between the first voltage state and the second voltage state, and is configured to make a voltage in the third voltage state changeable; and a controller that changes the voltage in the third voltage state to cause the driver unit to perform emphasis.

A differential signal receiver is provided. The differential signal receiver includes a first differential difference amplifier, a second differential difference amplifier, a latch and a first inverter. The first differential difference amplifier and the second differential difference amplifier compare a voltage value of an input signal with a first threshold value and a second threshold value, respectively, so as to output a first difference signal and a second difference signal, respectively. The second threshold value is an opposite value of the first threshold value. The latch has a set terminal for receiving the first difference signal and a reset terminal for receiving the second difference signal. The first inverter is configured to receive the first latch signal and output the first output signal. The first output signal has a duty cycle being the same as a duty cycle of the input signal.

Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.

Methods and apparatus are disclosed for communicating multiple logic states across a digital isolator. The digital isolator is a universal serial bus (USB) isolator in some embodiments. The digital isolator includes one or more single-bit data channels. Three or more logic states of information are transmitted across the single-bit data channel(s). The logic states are distinguished by a pulse sequence, and in particular a number of edges of the pulse sequence and a final value or final edge of the pulse sequence.

Methods and systems are described for obtaining a set of carrier-modulated symbols of a carrier-modulated codeword, each carrier-modulated symbol received via a respective wire of a plurality of wires of a multi-wire bus, applying each carrier-modulated symbol of the set of carrier-modulated symbols to a corresponding transistor of a set of transistors, the set of transistors further connected to a pair of output nodes according to a sub-channel vector of a plurality of mutually orthogonal sub-channel vectors, recovering a demodulation signal from the carrier-modulated symbols, and generating a demodulated sub-channel data output as a differential voltage on the pair of output nodes based on a linear combination of the set of carrier-modulated symbols by controlling conductivity of the set of transistors according to the demodulation signal.

A signal receiver includes a first transistor, a second transistor, a load circuit, an amplifying circuit and a load circuit. The first transistor has a first end receiving a power voltage, and a control end receive a first input signal. The second transistor has a first end receiving the power voltage, and a control end receiving a second input signal, wherein the first input signal and the second input signal are differential signals and transit between a first voltage and a reference ground voltage, the first voltage is larger than the power voltage. The load circuit is coupled to the first transistor and the second transistor. The amplifying circuit generates an output signal according a first signal on the second end of the first transistor and a second signal on the second end of the second transistor.

Systems and methods for implementation of modified decision feedback equalization. In one embodiment, a method, includes sweeping a reference voltage signal across a set of voltages to find a center point of an eye diagram, determining whether an asymmetry is present in the eye diagram relative to the center point of the eye diagram, and when an asymmetry is determined to be present, generating a control signal to select a mode of decision feedback equalization to be applied to an input data bit.

Methods and systems are described for obtaining a set of carrier-modulated symbols of a carrier-modulated codeword, each carrier-modulated symbol received via a respective wire of a plurality of wires of a multi-wire bus, applying each carrier-modulated symbol of the set of carrier-modulated symbols to a corresponding transistor of a set of transistors, the set of transistors further connected to a pair of output nodes according to a sub-channel vector of a plurality of mutually orthogonal sub-channel vectors, recovering a demodulation signal from the carrier-modulated symbols, and generating a demodulated sub-channel data output as a differential voltage on the pair of output nodes based on a linear combination of the set of carrier-modulated symbols by controlling conductivity of the set of transistors according to the demodulation signal.

Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.

A bias structure includes a reference voltage node connected to gate structures of a first NMOS transistor and a second NMOS transistor, a bias voltage node comprising a bias voltage, and a first op amp having a first input connected to the reference voltage, a second input connected to a drain of the first NMOS transistor, and an output connected to gate structures of a first PMOS transistor and a second PMOS transistor. The bias structure further includes a second op amp having a first input connected to the reference voltage, a second input connected to a drain of the second NMOS transistor, and an output connected to a gate structure of a third NMOS transistor and the bias voltage node. The first NMOS transistor matches a transistor of a differential pair of an integrated circuit device.