The disclosure provides a receiver and an automatic offset cancellation (AOC) method thereof. The receiver includes a receiving channel circuit and an AOC circuit. The receiving channel circuit generates an equalized differential signal including an equalized first-end signal and an equalized second-end signal according to an input differential signal. The AOC circuit detects a peak of the equalized first-end signal to generate a first peak detection result. The AOC circuit detects a peak of the equalized second-end signal to generate a second peak detection result. The AOC circuit compares the first peak detection result with the second peak detection result to generate a comparison result. The AOC circuit compensates a mismatch of an input differential pair in the receiving channel circuit according to the comparison result.

A configurable serial link interface circuit includes a first transceiver for coupling to a first serial link. The first transceiver includes a first transmit circuit to selectively drive first transmit data along the first serial link and a first receive circuit. The first receive circuit selectively receives first receive data along the first serial link. The interface includes a second transceiver for coupling to a second serial link. The second transceiver includes a second transmit circuit to selectively drive second transmit data along the second serial link, a second receive circuit to selectively receive second receive data along the second serial link, and control circuitry to control the selectivity of the first transmit circuit, the second transmit circuit, the first receive circuit and the second receive circuit. For a first mode of operation, the control circuitry configures the first and second transceivers to define a dual-duplex architecture. For a second mode of operation, the control circuitry configures the first and second transceivers to define a single-duplex architecture.

A programmable equalizer and related method are provided. The equalizer includes a pair of current-setting field effect transistors (FETs) coupled in series with a pair of input FETs and a pair of load resistors, respectively, between a first voltage rail (Vdd) and a second voltage rail (ground). A programmable equalization circuit is coupled between the sources of the input FETs, comprising a plurality of selectable resistive paths and a variable capacitor, which could also be configured as a plurality of selectable capacitive paths. Each of the selectable resistive paths (as well as each of the selectable capacitive paths) include a selection FET for selectively coupling the corresponding resistive (or capacitive) path between the sources of the input FETs. In the case where one of the input FETs is biased with a reference gate voltage, the source of each selection FET is coupled to the source of such input FET.

Described herein is a fully-differential receiver for use with an implantable medical device (IMD) and configured to receive conducted communication signals that are transmitted by another IMD or an external device. The fully-differential receiver includes a fully-differential preamplifier, a fully-differential buffer, a first comparator, a second comparator, and an AC coupling network coupled between differential outputs of the fully-differential buffer and a coupled together differential pair of inputs of the first and second comparators. A differential pair of inputs of the fully-differential receiver comprise the differential pair of inputs of the fully-differential preamplifier, and a differential pair of outputs of the fully-differential receiver comprise a first output of the first comparator and a second output of the second comparator. In order to conserve power, the fully-differential receiver is selectively changed from operating in a first mode to operating in a second mode, and vice versa.

Systems for bi-directional single-ended transmission are described. For example, a system may include a receiver with a first differential input terminal and a second differential input terminal, wherein the first differential input terminal is coupled to a first node and the second differential input terminal is coupled to a second node; a transmitter with an output terminal coupled to a third node; a first inductor connected between the first node and the third node; a second inductor connected between the second node and the third node; and a shunt resistor connected between the third node and a ground node.

Methods and systems are described for receiving signal elements corresponding to a first group of symbols of a vector signaling codeword over a first densely-routed wire group of a multi-wire bus at a first set of multi-input comparators (MICs), receiving signal elements corresponding to a second group of symbols of the vector signaling codeword over a second densely-routed wire group of the multi-wire bus at a second set of MICs, and receiving signal elements corresponding to the first and the second groups of symbols of the vector signaling codeword at a global MIC.

Aspects of the subject disclosure may include, for example, a coupling device includes a circuit that receives a signal. At least one passive electrical circuit element generates an electromagnetic field in response to the signal. A portion of the electromagnetic field is guided by a surface of a transmission medium to propagate as a guided electromagnetic wave longitudinally along the transmission medium. Other embodiments are disclosed.

Advanced detectors for vector signaling codes are disclosed which utilize multi-input comparators, generalized on-level slicing, reference generation based on maximum swing, and reference generation based on recent values. Vector signaling codes communicate information as groups of symbols which, when transmitted over multiple communications channels, may be received as mixed sets of symbols from different transmission groups due to propagation time variations between channels. Systems and methods are disclosed which compensate receivers and transmitters for these effects and/or utilize codes having increased immunity to such variations, and circuits are described that efficiently implement their component functions.

An interconnect module device is provided. The interconnect module device includes a line control command (LCC) detecting circuit configured to identify an LCC signal; an equalizer control circuit configured to generate a control signal based on the LCC signal; a receiving equalizer configured to perform receiving equalization on a first signal received from a first universal flash storage (UFS) device based on the control signal to generate a second signal; and a transmitting equalizer configured to perform transmitting equalization on the second signal to generate a third signal based on the control signal, and transmit the third signal to a second UFS device.

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.