In a Power over Data Lines (PoDL) system that conducts differential data and DC power over the same wire pair, various DC coupling techniques are described that improve DC voltage coupling while attenuating AC common mode noise and avoiding mode conversion. A first CMC and AC coupling capacitors are connected in series between a PHY and a twisted wire pair. A DC power supply is DC coupled to the wires via a series connection of a DMC and either matched inductors or a second CMC. Coupled between the DMC and the inductors/CMC is an RC termination circuit comprising a first capacitor coupled to one leg and a matched second capacitor coupled to the other leg. The two capacitors are connected to the same resistor coupled to ground.

The present invention is directed to communication systems and electrical circuits. According to an embodiment, the present invention provides a termination circuit that includes an inductor network. The inductor network is coupled to a termination resistor and a capacitor network, which includes a first capacitor and a second capacitor. The termination resistor, the first capacitor, and the second capacitor are adjustable, and they affect attenuation of the termination circuit. There are other embodiments as well.

An active termination circuit comprising an input node connected to a transmission line, a first transistor, and a second transistor. The transmission line supplies a signal to the input node. The first transistor is diode connected between a high voltage supply and the input node. The first transistor terminates the signal when the signal is at a low logic level. The second transistor is diode connected between the input node and a low voltage supply. The second transistor terminates the signal when the signal is at a high logic level.

A configurable serial link interface circuit includes a first transceiver for coupling to a first serial link. The first transceiver includes a first transmit circuit to selectively drive first transmit data along the first serial link and a first receive circuit. The first receive circuit selectively receives first receive data along the first serial link. The interface includes a second transceiver for coupling to a second serial link. The second transceiver includes a second transmit circuit to selectively drive second transmit data along the second serial link, a second receive circuit to selectively receive second receive data along the second serial link, and control circuitry to control the selectivity of the first transmit circuit, the second transmit circuit, the first receive circuit and the second receive circuit. For a first mode of operation, the control circuitry configures the first and second transceivers to define a dual-duplex architecture. For a second mode of operation, the control circuitry configures the first and second transceivers to define a single-duplex architecture.

A receiver includes a first T-coil circuit at an input of the receiver and configured to receive an input signal, a termination impedance coupled to the first T-coil circuit and configured to match an impedance of a transmission line coupled to the first T-coil circuit, and an amplifier including a first input and a second input and configured to amplify a differential signal at the first and second inputs, a calibration switch coupled to the amplifier and configured to selectively electrically connect or disconnect the first and second inputs of the amplifier, and a first receive switch configured to selectively electrically connect or disconnect a center node of the first T-coil circuit and the amplifier.

Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

A configurable serial link interface circuit is disclosed. The configurable serial link interface includes a first transceiver for coupling to a first serial link. The first transceiver includes a first transmit circuit to selectively drive first transmit data along the first serial link and a first receive circuit. the first receive circuit selectively receives first receive data along the first serial link. The interface includes a second transceiver for coupling to a second serial link. The second transceiver includes a second transmit circuit to selectively drive second transmit data along the second serial link, a second receive circuit to selectively receive second receive data along the second serial link, and control circuitry to control the selectivity of the first transmit circuit, the second transmit circuit, the first receive circuit and the second receive circuit. For a first mode of operation, the control circuitry configures the first and second transceivers to define a dual-duplex architecture. For a second mode of operation, the control circuitry configures the first and second transceivers to define a single-duplex architecture.

Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

A termination for a high-frequency transmission line includes a first resistor that has a first terminal coupled to a first end of a transmission line and a second terminal coupled to a first input/output pad, and a second resistor that has a first terminal coupled to the first input/output pad. The first resistor and the second resistor may provide a combined resistance that matches a nominal value of a characteristic impedance of the transmission line. The apparatus may include a third resistor having a first terminal coupled to a second end of a transmission line, and a second terminal coupled to a second input/output pad, and a fourth resistor having a first terminal coupled to the second input/output pad. The third resistor and the fourth resistor may provide a combined resistance that matches the nominal value of the characteristic impedance of the transmission line.

Memory devices might include an input/output (I/O) node, a termination device, an array of memory cells in communication with the I/O node through the termination device, and control circuitry, wherein the control circuitry is configured to compare an address received by the memory device to a plurality of instances of address information stored in the memory device. Each instance of address information of the plurality of instances of address information might correspond to a respective termination value stored in the memory device. In response to the memory device receiving an address matching an instance of address information stored in the memory device, the control circuitry might further be configured to activate the termination device using the respective termination value corresponding to the instance of address information matching the received address.