Patent classifications
H04L25/03006
Extremely compact phase-tracking 5G/6G reference signal
Precision synchronization is key to reliable communications at the high frequencies planned for 5G and 6G. A timing reference signal can provide a compact, resource-efficient, low-complexity phase noise mitigation while also providing an amplitude noise calibration. The timing reference signal is a QAM (quadrature amplitude modulation) signal with an I branch multiplexed with an orthogonal Q branch, in which one of the branches is modulated according to a maximum amplitude level of the modulation scheme, and the other branch has zero amplitude as-transmitted. When received, the amplitude and phase may be altered by noise. The receiver can measure the overall magnitude of the received I and Q signals to mitigate amplitude noise, and can also calculate a phase rotation angle according to a ratio of the I and Q branch signals as-received, and thereby correct for phase noise in the message.
Data synchronization in optical networks and devices
Joint estimation of the framer index and the frequency offset in an optical communication system are described among various other features. A transmitter can transmit data frames using pilot and framer symbols. A receiver can estimate the framer index and frequency offset using the pilot and framer symbols, and identify the beginning of a header portion of a data frame. By identifying the beginning of the header portion of a data frame, the receiver can then process data received from the transmitter in a manner synchronous to the manner in which the data was transmitted by the transmitter.
HETEROGENEOUS WEIGHTED OVERLAP-ADD WINDOWING AND FILTERING FOR ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING WAVEFORMS
Techniques for processing of symbols (e.g., orthogonal frequency division multiplexing (OFDM) or single carrier-frequency division multiple access (SC-FDMA) symbols) provide enhanced out-of-band (OOB) suppression of the symbols and also provide reduced inter-symbol interference (ISI) between a symbol and a subsequent symbol. Multiple frequency tones of a symbol may be divided into two or more subsets of tones. For example, subsets of tones associated with a head portion or a tail portion of an OFDM symbol may be processed with a relatively long weighted overlap-add (WOLA) weighting length or filtering length, and a subset of tones associated with a center portion of the OFDM symbol may be processed with a relatively short WOLA weighting length or filtering length. Such heterogeneous processing of tones within a symbol may provide enhanced inter-channel interference (ICI) and improved OOB suppression and also provide reduced ISI for the center tones of the symbol.
SILICON PHOTONICS BASED MODULE FOR EXECUTING PEER-TO-PEER TRANSACTIONS
An optical module configured to control a peer to peer transaction includes a silicon photonics substrate, memory formed on the silicon photonics substrate and configured to store a private key, application circuitry formed on the silicon photonics substrate and coupled to the memory, the application circuitry configured to receive, via an external interface, an electrical signal carrying instructions for executing a transaction, verify the transaction using the private key stored in the memory, and selectively generate a transaction message including information for completing the transaction, and optical communication circuitry formed on the silicon photonics substrate and responsive to the application circuitry, the optical communication circuitry configured to generate an optical signal based on the transaction message and transmit the optical signal to at least one remote entity.
OFFSET DETECTOR CIRCUIT FOR DIFFERENTIAL SIGNAL GENERATOR, RECEIVER, AND METHOD OF COMPENSATING FOR OFFSET OF DIFFERENTIAL SIGNAL GENERATOR
An offset detector circuit includes a digital signal register storing M unit digital signals received in latest M signal periods, M being a natural number, among digital signals generated based on a single-ended PAM-N signal, N being an odd number, a comparator outputting a comparison signal of a pair of signals included in differential signals generated from a differential signal generator based on the single-ended PAM-N signal, a comparison result register storing M unit comparison signals corresponding to the latest M signal periods among the comparison signals, a pattern detector outputting a detection signal when the M unit digital signals match a predetermined signal pattern, and an offset checker checking patterns of the M unit comparison signals in response to the detection signal, and outputting an offset detection signal when the patterns of the M unit comparison signals match a predetermined offset pattern.
Multimode interconnection interface controller for converged network
This invention discloses a multimode interconnection interface controller for a converged network, which comprises a SERDES element responsible for serial/parallel conversion, a LANE_TXCLK element responsible for generating a transmit clock, a SERDES initialization element responsible for link training and rate negotiation, and a PCS_EB coding element and an PCS_AF coding element responsible for physical layer coding of messages. The link training and rate negotiation are completed automatically via the shared SERDES initialization element. More universality and flexibility are provided for interconnection chip design by the PCS_EB coding element. The PCS_AF coding element is provided to reduce message penetration delay. The multimode interconnection interface controller is integrated in a single chip. Through flexible configuration, the single chip can meet transmission requirements of dedicated high speed networks and Ethernet networks. The multimode interconnection interface controller also supports interconnection of data center Ethernet and high performance computing high speed network.
COMMUNICATION DEVICE, COMMUNICATION METHOD THEREOF, INFORMATION PROCESSING DEVICE, CONTROL METHOD THEREOF, AND COMPUTER-READABLE STORAGE MEDIUM
A communication device communicates a radio frame including a preamble and a data field of a physical layer (PHY). The preamble includes an L-STF (Legacy Short Training Field), an L-LTF (Legacy Long Training Field), an L-SIG (Legacy Signal Field), an EHT-SIG-A (Extremely High Throughput Signal A Field), an EHT-STF, and an EHT-LTF, and the EHT-SIG-A includes a field indicating a standard that the radio frame complies with.
Allocating Partially Overlapping Resources to Communication Devices
A method of assigning transmission resources by an access node includes allocating first transmission resources to a first device, and allocating second transmission resources to a second device, wherein the second transmission resources partially, but not completely, overlap the first transmission resources. An amount of overlap between the first transmission resources and the second transmission resources may be based on a target error rate for decoding transmissions received from the first device and the second device and/or a signal to interference plus noise ratio (SINR) of transmissions from the first device and the second device. Related access nodes are disclosed.
METHOD FOR DETERMINING WHETHER TO DRIVE SYMBOL LEVEL INTERFERENCE CANCELLER
A disclosure of the present specification provides a method for determining whether to drive a symbol level interference canceller on the basis of a network support. The method comprises the steps of: determining whether to turn on the symbol level interference canceller on the basis of condition information on at least one between a serving cell and an interference cell; driving the symbol level interference canceller according to the determination; and determining whether to turn off the symbol level interference canceller, when the condition information has changed, while driving the symbol level interference canceller.
Maximum likelihood detector
The present invention discloses an ML (Maximum Likelihood) detector. An embodiment of the ML detector comprises a search value selecting circuit and an ML detecting circuit. The search value selecting circuit is configured to select a first-layer search value. The ML detecting circuit is configured to carry out the following steps: selecting first-layer candidate values according to the first-layer search value, one of a reception signal and a derivative thereof, and one of a channel estimation signal and a derivative thereof, and adding one or more first-layer candidate value(s), if necessary; calculating second-layer candidate values according to all the above-mentioned first-layer candidate values, and adding one or more second-layer candidate value(s) and its/their corresponding first-layer candidate value(s), if necessary; and calculating log likelihood ratios according to the whole first-layer and second-layer candidate values.