Patent classifications
H04L25/03828
DYNAMICALLY RECONFIGURABLE OVERSAMPLED CHANNELIZER
Techniques are provided for a dynamically reconfigurable two times (2) oversampled channelizer. A channelizer implementing the techniques according to an embodiment includes a polyphase filter, a two phase reorder circuit, a fast Fourier transform (FFT) circuit, and a two phase merge circuit. The polyphase filter is configured to filter time domain input data to control spectral shaping of frequency bins of the channelizer output. The two phase reorder circuit is configured to split a 2 oversampled data stream into two parallel, critically sampled data streams. The FFT circuit is configured to transform each stream into the frequency domain. The two phase merge circuit is configured to merge the two streams of frequency domain data into a single stream of 2 oversampled frequency domain data for distribution onto frames of frequency bins. Reconfigurable parameters for the channelizer include filter coefficients, number of filter folds, and number of frequency bins.
COMMUNICATION METHOD AND COMMUNICATION APPARATUS
Embodiments of this application disclose a communication method and a communication apparatus, to reduce a PAPR of a signal sent by a sending device by using an FDSS waveform processing manner, and reduce decoding power consumption of a receiving device by using a polar code encoding manner. This improves communication energy efficiency. In this method, the sending device performs frequency domain spectrum shaping FDSS processing on a first signal, to obtain a second signal, where the first signal is a signal obtained by performing polar code encoding based on a modulation and coding scheme; and then, the sending device sends a target signal to the receiving device, where the target signal is a signal obtained based on the second signal.
Systems and methods for on-chip filtering
Described are systems and methods take advantage of properties of sinc filters that remove frequency components at specific integer multiples of a noise frequency. In various embodiments, sampling of multi-channel systems at sufficiently high rates allows for removal of unwanted signals and harmonics from multi-sample sequences. Advantageously, a multi-sample sequence scheduling scheme eliminates the need for noise filtering one channel at a time at each channel's own sampling rate using a separate filter.
SIGNAL EQUALIZER AND SIGNAL EQUALIZING METHOD
A signal equalizer comprising: a feedback system, configured to acquire at least one signal value of an edge region of an input signal, and configured to adjust the signal value according to a crossing part of an eye diagram such that the crossing part converges to a zero point, wherein the crossing part corresponds to the edge region
Signal processing method and communications chip structure
This application discloses a communications chip structure, including: a channel selection module, configured to receive an input signal, where the input signal is a signal of a preset narrow bandwidth span or a signal of a preset wide bandwidth span; and a digital baseband module, configured to control the channel selection module to select a first sampling and quantification channel when the input signal is a signal of the preset narrow bandwidth span, or control the channel selection module to select a second sampling and quantification channel when the input signal is a signal of the preset wide bandwidth span. The channel selection module is further configured to send the input signal to the first sampling and quantification channel or the second sampling and quantification channel for sampling and quantification.
Multipath bandpass filters with passband notches
Apparatus and methods related to multipath bandpass filters with passband notches are provided herein. In certain configurations, a multipath bandpass filter includes multiple filter circuit branches or paths that are electrically connected in parallel with one another between an input terminal and an output terminal. The input terminal receives an input signal, and each filter circuit branch includes a downconverter that downconverts the input signal to generate a downconverted signal, a filter network that generates a filtered signal by filtering the downconverted signal, and an upconverter that upconverts the filtered signal to generate a branch output signal. The filter network includes at least one low pass filter and at least one notch filter to provide a passband with in-band notches. The branch output signals from the filter circuit branches are combined to generate an output signal at the output terminal.
Apparatus and method for de-embedding a combiner from a balanced signal
A test and measurement system including a plurality of channels and one or more processors. The one or more processors are configured to cause the test and measurement system to receive, via a first channel of the plurality of channels, a positive side of a reference differential signal pair, receive, via a second channel of the plurality of channels, a negative side of the reference differential signal pair, and produce a reference signal based the reference differential signal pair. A combined signal is received, from a combiner, that is a balanced signal produced from the reference differential signal pair. A de-embed filter is generated based on the reference signal and the combined signal and an additional signal is received from the combiner and an effect of the combiner is removed from the additional signal by applying the de-embed filter to the additional signal.
Semiconductor device and memory system
A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.
METHOD FOR COMPENSATING GAIN FLATNESS OF TRANSCEIVER
The present disclosure provides a method for compensating gain flatness of a transceiver including: a method for compensating gain flatness of a receiver, which compensates gain flatness of a receiving channel by using a complex-coefficient FIR filter in digital domain; and a method for compensating gain flatness of a transmitter, which compensates gain flatness of a transmitting channel by using a complex-coefficient FIR filter in digital domain. The method according to the present disclosure can balance compensation accuracy and calculation amount flexibly, and can focus on compensating the gain flatness at an edge of a frequency band, obtaining good performance with less calculation amount.
Feedback based on codebook subset
The present invention provides for an improved application of signal strength weightings in a SDMA sectorized cellular network. The improved signal strength weightings application is conducted through the improved selection of weightings from a new codebook subset or by the selection of weightings from a larger codebook subset. In a further embodiment, an antenna beam index or bit map can be used to select the best beam(s) in a SDMA sectorized cellular network. In another embodiment, a field or factor in an uplink or downlink transmission packet can designate which directional transmission beam is best suited for the transmission or when the directional transmission beam should be activated.