An equalizer that has a wide variable gain range and that can implement equalization for a communication medium such as on-board wiring or a cable having various wiring lengths. The equalizer includes a core circuit and a source follower connected to a subsequent stage of the core circuit. The core circuit includes a differential pair including a first transistor and a second transistor, and a zero point generation circuit connected between a second terminal of the first transistor and a second terminal of the second transistor. The source follower includes a third transistor and a fourth transistor, a variable bias current source is connected to the third and fourth transistors, and a load in which a capacitive element and a resistor element are connected in series via a switching element is connected to wiring that connects the third and fourth transistors to an output terminal.

A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC) and a second DAC. The first DAC includes a first current generation circuit (CGC) and a first current-to-voltage converter. The first CGC generates a first current based on a first digital code received through a first terminal to provide the first current to an output node. The second DAC includes a second CGC and a second current-to-voltage converter. The second CGC generates a second current based on a second digital code received through a second input terminal to provide the second current to the output node. The first current-to-voltage converter and the second current-to-voltage converter convert a sum of the first current and the second current to a an analog voltage corresponding to a sum of the first digital code and the second digital code, and output the analog voltage at the output node.

A receiving circuit of a deserializer is provided. The receiving circuit of the deserializer receives an input signal and includes: a signal receiving terminal for receiving the input signal; a link equalizer circuit (LEQ) having a first input terminal coupled to the signal receiving terminal; and an out-of-band signaling (OOBS) circuit having a second input terminal coupled to the signal receiving terminal; a first resistor coupled between the signal receiving terminal and a first reference voltage; and a second resistor coupled between the signal receiving terminal and a second reference voltage; and a buffer circuit having a third input terminal and an output terminal, wherein the third input terminal receives a voltage, and the output terminal is coupled to the LEQ or the OOBS circuit. The first input terminal of the LEQ and the second input terminal of the OOBS circuit are not electrically coupled, and the voltage is adjustable.

Transmit-side equalization is disclosed for network devices and network communications methods employing onboard/co-packaged optics. An illustrative network device includes a substrate having a host device IC (integrated circuit) and an optical module IC connected by a short-reach link. The optical module IC having a transmit chain includes a CTLE (continuous time linear equalizer) to at least partly compensate for a channel response of the short-reach link, and a driver that amplifies an output of the CTLE for a photoemitter that couples to an optical fiber. The host device IC includes: a parallel-to-serial converter that produces a digital symbol stream; a digital to analog converter that supplies an analog signal to the short-reach link; and a pre-equalizer coupling the parallel-to-serial converter to the digital-to-analog converter, the pre-equalizer filtering the digital symbol stream to at least partly compensate for a channel response of a combined channel that includes the short-reach link, the CTLE, the driver, and the photoemitter.

A device receives network information from an analyzer device associated with a host device, a target device, and a link of a network, and compares the network information and historical equalizer calibration information to identify a set of equalizer calibration information. The historical equalizer calibration information is associated with multiple host devices, multiple target devices, and multiple links. The device ranks the set of equalizer calibration information, based on quality information associated with the historical equalizer calibration information, to generate a ranked set of equalizer calibration information. The device provides the ranked set of equalizer calibration information to the analyzer device to permit the analyzer device to identify selected equalizer calibration information of the ranked set of equalizer calibration information, and utilize the selected equalizer calibration information.

According to one embodiment, in a semiconductor integrated circuit, a sampler is connected to an output node of a summer circuit. A shift register is connected to an output node of the sampler and includes K stages of registers, K being an integer that is equal to or larger than 3. To a control circuit, output nodes of respective registers of N-th to M-th stages among the K stages of registers are connected, N being an integer larger than 1 and smaller than K, M being an integer larger than N and equal to or smaller than K. A first switch includes one end connected to the output node of the summer circuit. A correction circuit includes a first control node that is connected to the control circuit through a first feedback line and an output node to which a second end of the first switch is connected.

A latch circuit and an equalizer including the same are provided. The equalizer includes: an even data path configured to receive a reception data signal and including a first summing circuit and a first latch circuit; and an odd data path configured to receive the reception data signal and including a second summing circuit and a second latch circuit. An even data signal output from the first latch circuit is configured to be input to the second summing circuit, and an odd data signal output from the second latch circuit is configured to be input to the first summing circuit. Each of the first latch circuit and the second latch circuit includes a latch and a multiplexer.

A method of manufacturing an RF switch includes adding a first mutual inductance portion to a first self-inductance portion of a first transmission line; and adding a second mutual inductance portion to a second self-inductance portion of a second transmission line, wherein values of the first and second mutual inductance portions and values of the first and second self-inductance portions equalize an impedance difference between the first transmission line and the second transmission line.

A signal transmission circuit element, a multiplexer circuit element and a demultiplexer circuit element are disclosed. The signal transmission circuit element is connected among multiple electronic modules so as to transmit an electrical signal. The signal transmission circuit element includes an input terminal, an input equalizer, an output driver and an output terminal. The input terminal is for inputting an electrical signal to the input equalizer. The output driver is electrically connected to the input equalizer. The output terminal is electrically connected to the output driver so as to output the electrical signal. Accordingly, after the input terminal receives the electrical signal, the input equalizer can perform gain compensation on the electrical signal, and then an output capacitance of the electrical signal is driven by the output driver and outputted through the output terminal.

A method of equalizing a communication link includes setting a number of coefficients equal to a required number of coefficients, determining a number of pulse responses for a waveform, the number of pulse responses being greater than the number of coefficients, setting all values in a set of values to zero, the set of values having a number of values equal to the number of coefficients, repeating, until all values in the set of values have been assigned, determining a current lowest parameter in a set of given parameters, using a position of the current lowest parameter in the set of given parameters as an index, determining a minimum value between a first term in the set of given parameters multiplied by a main pulse response minus a summation of each parameter in the set of parameters multiplied by each value in the set of values, divided by the current lowest parameter, and a corresponding pulse response, and assigning the minimum value to the value in the set of values having a position equal to position of the current lowest parameter, and determining a value of each coefficient in a set of coefficients by multiplying each value in the set of values with the sign of a corresponding pulse response in the number of pulse responses; defining an equalizer having a number of taps equal to the number of coefficients, each tap having a value based on the corresponding coefficient; and applying the equalizer to a waveform received through the communication link to produce an equalized waveform. A test and measurement device is also disclosed.