Methods and systems for channel estimation using iterative channel tracking algorithm, in a communication system combined multiple input multiple output (MIMO) technology with orthogonal frequency division multiplexing (OFDM), are disclose. The initial channel estimation of a data packet uses the first preamble inserted in front of the OFDM blocks. After demodulating subsequent one or more OFDM blocks, iterative channel tracking method is used for channel estimation until the next preamble is received. The iterative channel tracking is based on the received signals and the demodulated results of subsequent one or more OFDM blocks.

Systems and methods for providing offset calibration for low power and high performance receivers are described herein. In one embodiment, a receiver comprises a sample latch having a first input coupled to a receive data path, and a second input. The receive also comprises a first digital-to-analog converter (DAC), a second DAC, and a calibration controller. In a calibration mode, the calibration controller is configured to input a calibration voltage to the first input of the sample latch using the first DAC, to input a threshold voltage and an offset-cancelation voltage to the second input of the sample latch using the second DAC, to adjust the offset-cancelation voltage, to observe an output of the sample latch as the offset-cancelation voltage is adjusted, and to store a value of the offset-cancelation voltage at which a metastable state is observed at the output of the sample latch in a memory.

A signal processing device includes: an extraction section configured to extract a signal having a predetermined component from an obtained signal; and a detection section configured to determine a timing of decoding when a modulation part lasting for a first time period and a non-modulation part lasting for a second time period are detected from the signal extracted by the extraction section.

A receiver includes a plurality of equalization modules each configurable to provide a selectable compensation value to a data bit stream received by the receiver, and a control module configured to perform a plurality of back channel adaptations on the data bitstream to achieve a target bit error rate for the receiver, each back channel adaptation being associated with a set of compensation values of the equalization modules, determine a most common set of compensation values derived from the performance of the plurality of back channel adaptations, and determine an optimized set of compensation values based on the most common set of compensation values.

An antenna front-end module, method, and information handling system are adapted to the application of a direct-current (DC) bias voltage in relation to an antenna and detect a connection status of the antenna based on a sensed DC voltage. When the connection status corresponds to the antenna being connected, a first transmit power level is configured. When the connection status corresponds to the antenna being disconnected, a second transmit power level is configured. A transmit power boost can be provided such that the first transmit power level is greater than the second transmit power level. The first transmit power level can correspond to a radiative transmission mode, and the second transmit power level can correspond to a conductive transmission mode.

A baud-rate phase detector uses two error samplers. One error sampler is used to determine whether the sampling time is too early error detection. The other is used to determine whether sampling time is too late. The early error sampler is configured to use a first threshold voltage. The late error sampler is configured to use a second threshold voltage. By adjusting the voltage difference between the first threshold voltage and the second threshold voltage, the phase difference between the local timing reference clock and the transitions of the data signal may be adjusted. The phase difference between the local timing reference clock and the transitions of the data signal may be adjusted to improve or optimize a desired receiver characteristic such as bit error rate or signal eye opening.

A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

There is provided a clock and data recovery circuit for a high-speed PAM-4 receiver through statistical learning. A clock and data recovery device according to an embodiment includes: an input unit through which data is inputted; a clock input unit through which a clock is inputted; a sampling unit configured to sample the inputted data by using the inputted clock; a controller configured to combine results of sampling at a plurality of sampling points, to determine a state of the clock based on the combined results, and to generate a control value for controlling the clock; and an adjustment unit configured to adjust the clock applied to the sampling unit, based on the control value generated by the controller. Accordingly, a hardware structure is simplified and energy efficiency is enhanced compared to an exiting oversampling clock and data recovery circuit for a PAM-4 receiver.

A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.

This disclosure provides systems, methods and apparatuses for wireless communications. In some implementations, a first wireless communication device associated with a basic service set (BSS) receives a plurality of packets transmitted during a measurement window by a second wireless communication device associated with the BSS. The first wireless communication device determines a received signal strength indicator (RSSI) value of the plurality of received packets, determines a level of overlapping basic service set (OBSS) interference on the wireless medium during the measurement window, and adjusts one or more of a packet detect (PD) threshold, an OBSS PD threshold, or an energy detect (ED) threshold based on the determined RSSI value and the level of OBSS interference.