There is provided a clock and data recovery circuit for a high-speed PAM-4 receiver through statistical learning. A clock and data recovery device according to an embodiment includes: an input unit through which data is inputted; a clock input unit through which a clock is inputted; a sampling unit configured to sample the inputted data by using the inputted clock; a controller configured to combine results of sampling at a plurality of sampling points, to determine a state of the clock based on the combined results, and to generate a control value for controlling the clock; and an adjustment unit configured to adjust the clock applied to the sampling unit, based on the control value generated by the controller. Accordingly, a hardware structure is simplified and energy efficiency is enhanced compared to an exiting oversampling clock and data recovery circuit for a PAM-4 receiver.

A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.

A driver circuit of a PAM-N transmitting device transmits a PAM-N signal via a communication channel, wherein N is greater than 2, and the PAM-N signal has N signal levels corresponding to N symbols. A PAM-N receiving device receives the PAM-N signal. The PAM-N receiving device generates distortion information indicative of a level of distortion corresponding to inequalities in voltage differences between the N signal levels. The PAM-N receiving device transmits to the PAM-N transmitting device the distortion information indicative of the level of the distortion. The PAM-N transmitting device receives the distortion information. The PAM-N transmitting device adjusts one or more drive strength parameters of the driver circuit of the PAM-N transmitting device based on the distortion information.

An FPGA based system for decoding PAM-3 signals is disclosed, wherein the system comprises a directional coupler for separating 100BASE-T1 and 1000BASE-T1 master and slave signals, DVGAs for amplifying the master and slave signals, ADCs for sampling the amplified signals, and a FPGA module, wherein the FPGA module is configured for decoding the PAM-3 symbols, in real-time, from oversampled ADCs data using fully pipelined Register Transfer Level (RTL) architecture.

The present specification provides a method for transmitting a signal in a wireless communication system. More specifically, the method performed by a transmission terminal comprises the steps of: generating at least one bit into a complex symbol by using a modulation scheme; mapping the complex symbol to subcarriers each having an even index or subcarriers each having an odd index among subcarriers of at least one configured resource block; performing IFFT on the subcarriers to which the complex symbol is mapped, in order to generate a time-continuous signal; performing a DC bias on the time-continuous signal; and transmitting the DC biased signal.

Systems and methods for enabling pre-compensation of timing offsets in OFDM receivers without invalidating channel estimates are described. Timing offset estimations may be sent along with the received OFDM symbols for FFT computation and generating a de-rotated signal output. The timing offset estimation may provide a reference point for dynamic tracking of timing for an OFDM signal and estimated based on an integral value associated with the OFDM signal.

An FPGA based system for decoding PAM-3 signals is disclosed, wherein the system comprises a directional coupler for separating 100BASE-T1 and 1000BASE-T1 master and slave signals, DVGAs for amplifying the master and slave signals, ADCs for sampling the amplified signals, and a FPGA module, wherein the FPGA module is configured for decoding the PAM-3 symbols, in real-time, from oversampled ADCs data using fully pipelined Register Transfer Level (RTL) architecture.

An antenna front-end module, method, and information handling system are adapted to the application of a direct-current (DC) bias voltage in relation to an antenna and detect a connection status of the antenna based on a sensed DC voltage. When the connection status corresponds to the antenna being connected, a first transmit power level is configured. When the connection status corresponds to the antenna being disconnected, a second transmit power level is configured. A transmit power boost can be provided such that the first transmit power level is greater than the second transmit power level. The first transmit power level can correspond to a radiative transmission mode, and the second transmit power level can correspond to a conductive transmission mode.

To more efficiently compensate for modulation imbalance, a mobile device modulates and demodulates a calibration tone and generates digital data representing modulation imbalance effects on the calibration tone. Using digital data enables modulation imbalance effects to be quickly estimated using digital signal processing techniques, increasing the number of estimates of modulation imbalance effects calculated. The modulation imbalance estimates are used to refine one or more compensation parameters which are applied to transmitted and/or received signals to compensate for errors caused by modulation.

A system includes a data carrier drive apparatus and a data carrier apparatus. The data carrier apparatus includes: an unit configured to output transmission data during a first state and adjustment data during a second state; and a current changer configured to change a current value of a current flowing from the data carrier drive apparatus to the data carrier apparatus according to data values of the transmission data and the adjustment data. The data carrier drive apparatus includes: a detector configured to detect a detection value corresponding to the current value of the current; a determiner configured to determine the data value of the transmission data by comparing the detection value with a threshold value during the first state; and an updater configured to update the threshold value based on the detection value during the second state.