The telemetry system used in the measurement while drilling (MWD) or logging while drilling (LWD) is essentially a digital communication system. The fact of the special and hostile drilling environment limits the use of many advanced techniques and equipment, and thus results in a low data transmission rate. While increasing the data rate for the MWD/LWD telemetry system becomes a primary focus, maintaining the system reliability and the decoding quality at a high data rate is equally challenging. This invention presents digital signal processing solutions to a high performance telemetry system with the high data rate, high system reliability, and high decoding quality.

A method and receiver are disclosed for the blind detection and synchronization of data packets are disclosed. According to one aspect, a method includes generating a running histogram of received sample values for each of a plurality of frequency bins and symbol timing phases, the running histogram spanning a most recent block of symbols representing a candidate synchronization (sync) word. The method also includes, for each symbol interval: analyzing the histogram to estimate symbol timing phase, DC offset and frequency offset. The method also includes determining a first candidate sync word based at least in part on the symbol timing phase, frequency offset and corresponding DC offset the first candidate sync word representing a most recent vector of bits associated with the first candidate sync word. The method further includes discerning a lower address part (LAP) obtained from the first candidate sync word to enable detection of a packet.

Described herein is an improved apparatus for increasing the performance of a modulator, which may function as an ADC. In one embodiment, the modulator comprises a voltage to current converter, a capacitor connected between two outputs of the voltage to current converter to receive a differential input current, and a switch that can switch between connecting each output of the voltage to current converter to ground while disconnecting the other output of the voltage to current converter. In this embodiment, the modulator has no common mode control loop, and no reference current. This results in decreased complexity, i.e., fewer components, as well as reduced noise.

A device for determining a DC component in a zero-IF radio receiver comprises an input configured to receive a complex baseband signal; and an analyzer configured to analyze the complex baseband signal to determine a DC component in the complex baseband signal by selecting at least three samples of the complex baseband signal and determining the intersection of at least two perpendicular bisectors of at least two straight lines, each straight line running through a different pair of two of said selected samples, said intersection representing the DC component. Further, a corresponding method, a radar device and a radar method are disclosed.

A communication device configured to operate in accordance with a first communication protocol and to align itself with one or more communications transmitted in accordance with that protocol by identifying a communication transmitted in accordance with a second communication protocol that is not intended for the communication device, deriving alignment information from the identified communication and configuring itself to receive a communication transmitted in accordance with the first communication protocol in dependence on the alignment information.

Disclosed herein are related to a system and a method for high speed communication. In one aspect, the system includes a set of slicers configured to generate a slicer output signal digitally indicating a level of an input signal received by the set of slicers. The system includes a speculative tap coupled to the set of slicers, where the speculative tap is configured to select bits of the slicer output signal based on selected bits of a prior slicer output signal. The system includes a decoder coupled to the speculative tap, where the decoder is configured to decode the selected bits of the slicer output signal in a first digital representation into a second digital representation. The system includes a feedback generator coupled to the decoder, where the feedback generator is configured to generate a feedback signal according to the decoded bits of the slicer output signal.

A stable modulation-index Bluetooth (BT) transmitter circuit includes a baseband modulator circuit to generate a baseband BT signal. An intermediate frequency (IF) circuit adds a frequency offset to the baseband BT signal with a low IF and generates a modulated signal. A digital-to-analog converter (DAC) converts the modulated signal to an analog signal that is upconverted using a voltage controlled oscillator (VCO). The baseband frequency offset is subtracted from the corresponding radio-frequency (RF) signal by reducing the local oscillator (LO) frequency by the same amount. This has the effect of modulating the carrier leakage away from the center frequency of the transmitted BT signal. The resulting RF signal is transmitted to a receiver.

A stable modulation-index Bluetooth (BT) transmitter circuit includes a baseband modulator circuit to generate a baseband BT signal. An intermediate frequency (IF) circuit adds a frequency offset to the baseband BT signal with a low IF and generates a modulated signal. A digital-to-analog converter (DAC) converts the modulated signal to an analog signal that is upconverted using a voltage controlled oscillator (VCO). The baseband frequency offset is subtracted from the corresponding radio-frequency (RF) signal by reducing the local oscillator (LO) frequency by the same amount. This has the effect of modulating the carrier leakage away from the center frequency of the transmitted BT signal. The resulting RF signal is transmitted to a receiver.

A method and receiver are disclosed for the blind detection and synchronization of data packets are disclosed. According to one aspect, a method includes generating a running histogram of received sample values for each of a plurality of frequency bins and symbol timing phases, the running histogram spanning a most recent block of symbols representing a candidate synchronization (sync) word. The method also includes, for each symbol interval: analyzing the histogram to estimate symbol timing phase, DC offset and frequency offset. The method also includes determining a first candidate sync word based at least in part on the symbol timing phase, frequency offset and corresponding DC offset the first candidate sync word representing a most recent vector of bits associated with the first candidate sync word. The method further includes discerning a lower address part (LAP) obtained from the first candidate sync word to enable detection of a packet.

Disclosed herein are related to a system and a method for high speed communication. In one aspect, the system includes a set of slicers configured to generate a slicer output signal digitally indicating a level of an input signal received by the set of slicers. The system includes a speculative tap coupled to the set of slicers, where the speculative tap is configured to select bits of the slicer output signal based on selected bits of a prior slicer output signal. The system includes a decoder coupled to the speculative tap, where the decoder is configured to decode the selected bits of the slicer output signal in a first digital representation into a second digital representation. The system includes a feedback generator coupled to the decoder, where the feedback generator is configured to generate a feedback signal according to the decoded bits of the slicer output signal.