A digital isolator can include: an encoding circuit configured to receive an input digital signal, and to generate an encoded signal according to the input digital signal; an isolation element having a primary winding, a first secondary winding, and a second secondary winding; a differential circuit configured to receive first and second differential signals, and to generate a difference signal according to the first and second differential signals; and a decoding circuit coupled with the differential circuit, and being configured to receive the difference signal, and to generate a target digital signal after decoding.

A digital isolator can include: an encoding circuit configured to receive an input digital signal, and to generate an encoded signal according to the input digital signal; an isolation element having a primary winding, a first secondary winding, and a second secondary winding; a differential circuit configured to receive first and second differential signals, and to generate a difference signal according to the first and second differential signals; and a decoding circuit coupled with the differential circuit, and being configured to receive the difference signal, and to generate a target digital signal after decoding.

The invention discloses a transmitter comprising a pulse encoder for creating pulses from the amplitude of an input signal to the transmitter, a compensation signal generator for cancelling quantization noise caused by the pulse encoder, a mixer or I/Q modulator for mixing an output of the pulse encoder with the phase of an input signal to the transmitter, said output of the pulse encoder comprising the amplitude of the complex input signal plus the quantization noise caused by the pulse encoder, and an amplifier for creating an output signal from the transmitter. In the transmitter, a control signal (C.sub.A) for controlling a function of the amplifier comprises an output signal from the compensation signal generator, and an input signal to the amplifier comprises an output from the mixer having been modulated to a desired frequency.

The invention discloses a transmitter comprising a pulse encoder for creating pulses from the amplitude of an input signal to the transmitter, a compensation signal generator for cancelling quantization noise caused by the pulse encoder, a mixer or I/Q modulator for mixing an output of the pulse encoder with the phase of an input signal to the transmitter, said output of the pulse encoder comprising the amplitude of the complex input signal plus the quantization noise caused by the pulse encoder, and an amplifier for creating an output signal from the transmitter. In the transmitter, a control signal (C.sub.A) for controlling a function of the amplifier comprises an output signal from the compensation signal generator, and an input signal to the amplifier comprises an output from the mixer having been modulated to a desired frequency.

A system for communicating information between circuits is described. A transmit circuit provides pulse-amplitude-modulation (PAM) signals via a communication channel to a receiver. A circuit in the receiver determines digital values from the received signals using a time-varying threshold voltage, which varies during the bit-time. This approach may compensate for inter-symbol interference (ISI) to increase the voltage and timing margins of the system.

An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herein called the “ISI Ratio” are described which permit higher communications speed, lower system power consumption, and reduced implementation complexity.

The invention relates to a method for the secured digital transmission of current measurement values and to a battery (1) and a battery controller (10) which are suitable for carrying out the method. The method has the steps of detecting (S1, S2) an amplitude of a battery current (I.sub.B) in a battery (1) using a first and a second sensor (2, 3), generating (S3, S4) a first and a second bit sequence, each of which describes the detected amplitude, generating a mirrored second bit sequence (21) by reversing (S5) a sequence of the bits provided by the second bit sequence (20), simultaneously transmitting (S6) the first bit sequence via a first data bus (5) and the mirrored second bit sequence (21) via a second data bus (6) to a battery controller (10), generating a second bit sequence (20) by reversing (S7) a sequence of the bits provided by the mirrored second bit sequence (21) after the simultaneous transmission (S6), and finally detecting (S8) a possible error in the first bit sequence or the second bit sequence (20) by comparing the first bit sequence (20) with the second bit sequence (21). Transmission faults are thus detected in particular in a transmission path between the sensors of the battery and the battery controller, said faults being caused by a common disturbance. Additionally, faults can also be detected which are caused by a disturbance that only affects one of the sensors or a part of the transmission path.

Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.

A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.

A digital frontend circuit for a radio frequency (RF) comprises a digital predistortion (DPD) block, a plurality of sub-sample delay elements, and a selection circuit. The DPD block for computing predistorted transmit signals according to a Volterra series approximation model. The DPD block has an input for receiving input samples at a first sample rate and an output for providing the predistorted transmit signals at the first sample rate. Each of the sub-sample delay elements provides a delay to an input sample as specified by the Volterra series approximation model, where each of the delays is based on a fraction of the first sample rate. The selection circuit selects one of the plurality of sub-sample delay elements in response to a selection signal from the digital predistortion block. The selection signal for selecting a delay as specified by the Volterra series approximation model.