H04L25/49

Method for measuring and correcting multi-wire skew

Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

Method for measuring and correcting multi-wire skew

Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

Surgical helmet

Implementations described herein include surgical helmet assemblies that have a helmet enclosure shaped to encircle a head of a user. The helmet enclosure retains a fan and includes a brow bar portion at a front of the helmet enclosure that is shaped to extend along a brow or a forehead of the user and having a light positioned therein. The helmet enclosure also includes a stabilizer extending downward from the helmet enclosure in front of the ears of a user, a face shield that is transparent and coupleable to at least the brow bar portion, a headband shaped to extend across an occiput region of the user's head, and a surgical garment for covering at least the head and shoulders of a user in use. The brow bar portion includes vents disposed therein to direct airflow pushed through the helmet enclosure from the fan onto the user. The face shield is coupleable to the helmet enclosure by one or more of a hook and loop fastener on the helmet enclosure or the stabilizer and a post protruding from the brow bar portion.

Pulse-amplitude modulation transceiver, field device and method for operating the pulse-amplitude modulation transceiver

A PAM transceiver configured to process an electrical data signal having at least three states includes an electronic circuit comprising: a data interface configured to connect to a duplex communication channel; a first circuit section connected to the data interface; and a second circuit section connected to the data interface. The first circuit section includes an equalizer for compensating for distortions in the data signal and an interpreter downstream of the equalizer for recognizing symbols. The second circuit section includes a delay unit for time-shifting the data signal and an MMA processor for recognizing a signal phase of the data signal. The first circuit section and the second circuit sections are routed to the MMA processor. The second circuit section has a finite impulse response filter configured to monotonize an impulse response of the communication channel.

Optical encoder capable of identifying positions based on PWM signals
11799699 · 2023-10-24 · ·

The present disclosure is related to an optical encoder which is configured to provide precise coding reference data by feature recognition technology. To apply the present disclosure, it is not necessary to provide particular dense patterns on a working surface. The precise coding reference data can be generated by detecting surface features of the working surface.

Systems and methods for ultra wideband impulse radio protocols

Ultra-Wideband (UWB) technology exploits modulated coded impulses over a wide frequency spectrum with very low power over a short distance for digital data transmission. Today's leading edge modulated sinusoidal wave wireless communication standards and systems achieve power efficiencies of 50 nJ/bit employing narrowband signaling schemes and traditional RF transceiver architectures. However, such designs severely limit the achievable energy efficiency, especially at lower data rates such as below 1 Mbps. Further, it is important that peak power consumption is supportable by common battery or energy harvesting technologies and long term power consumption neither leads to limited battery lifetimes or an inability for alternate energy sources to sustain them. Accordingly, it would be beneficial for next generation applications to exploit inventive transceiver structures and communication schemes in order to achieve the sub nJ per bit energy efficiencies required by next generation applications.

Apparatuses and methods for encoding and decoding of signal lines for multi-level communication architectures
11809715 · 2023-11-07 ·

Apparatuses and methods for multi-level communication architectures are disclosed herein. An example apparatus may include a driver circuit configured to convert a plurality of bitstreams into a plurality of multilevel signals. A count of the plurality of bitstreams is greater than count of the plurality of multilevel signals. The driver circuit further configured to drive the plurality of multilevel signals onto a plurality of signal lines using individual drivers. A driver of the individual drivers is configured to drive more than two voltages.

Transmission device, transmission method, receiving device, and receiving method for performing signal transmission between a plurality of daisy chained devices

To enable preferable signal transmission between a plurality of daisy-chained devices at low cost. A transmission device generates a plurality of signals having different voltage levels and outputs the signals to a communication line at different timings. For example, the plurality of signals having different voltage levels is generated by a plurality of drivers or one driver. A receiving side can immediately determine whether or not it is information to be passed to the subsequent stage on the basis of only a difference in voltage level without logically analyzing contents of a signal, and cost of components such as a memory, verification cost, or the like are unnecessary so that the cost can be reduced.

PAM-4 DFE ARCHITECTURES WITH SYMBOL-TRANSITION DEPENDENT DFE TAP VALUES

Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.

MULTI-MODE LINE DRIVER CIRCUIT FOR THE PHYSICAL LAYER OF A NETWORK CONNECTION, PARTICULARLY OF AN ETHERNET COMMUNICATION, SUPPORTING DIFFERENT SIGNAL LEVELS FOR DIFFERENT COMMUNICATION STANDARDS

A multi-mode line driver circuit supporting different communication standards includes an output for the network connection, and driver elements connected in parallel to the output. Each driver element is connected to a positive and negative supply voltage, and includes a resistor, a first switch and a second switch. The resistor is connected to the output and via the first switch to the positive supply voltage and via the second switch to the negative supply voltage. The driver circuit also includes at least one coding block with an input for a digital signal to be transmitted over the network connection. The coding block provides control signals for the first switch and the second switch for connecting the resistor of each driver element to the positive supply voltage or the negative supply voltage. The digital signal of the multi-mode line driver circuit is coded according to a communication standard.