Disclosed is an ECU that transmits a pulse signal with a modulated frequency and duty cycle to a BMS so as to instruct a switching operation of a control target relay from among a plurality of relays and a BMS to control a switching operation of the corresponding relay according to the modulating pulse signal received from the ECU and control a first voltage change period to a communication line.

Some embodiments include apparatuses and methods having a component to change a value of a bit among a number of M bits of information when the M bits have the same value and when M exceeds a selected value. At least one of such embodiments can include a transmitting component to provide the information to a connection. At least one of such embodiments can include a receiving component to receive the information from the connection. In at least one of such embodiments, the selected value can include a maximum number of consecutive bits having the same value that such a receiving component can be configured to receive. Other embodiments including additional apparatuses and methods are described.

A reference voltage generation device includes a noise information generation circuit configured to generate power noise information based on a first power noise and a second power noise, the first power noise and the second power noise generated based on a first power and a second power supplied to a first electronic device and propagated from the first electronic device to a second electronic device through a communication line, and the first electronic device and the second electronic device configured to perform data communication using a multi-level signaling scheme. The device includes a reference voltage generation circuit configured to generate three or more reference voltages for the multi-level signaling scheme based on the power noise information, and the second electronic device is configured to use the three or more reference voltages.

A method of communicating information from a sensor concerning a received signal, comprising: responsive to receiving by at least one detecting sensor, during a defined time interval, data indicative of an entire data of a frequency band received by it during the defined time interval, comprising at least one signal emitted at least one emitter, and to detecting of the emitted signal by the at least one detecting sensor, sending from the sensor assistance information corresponding to the detected emitted signal during the defined time interval, to at least one non-detecting sensor. This information can be utilized by the non-detecting sensor to perform an action with respect to data indicative of an entire data of the frequency band received by the non-detecting sensor during a corresponding defined time interval, the action corresponding to at least one emitted signal received by the non-detecting sensor during the corresponding defined time interval.

Systems, methods, and apparatus for error signaling on a serial bus are described. An apparatus includes a bus interface configured to couple the apparatus to a serial bus, a phase-differential decoder configured to decode data from transitions between pairs of symbols in a sequence of symbols received from the serial bus, each symbol being representative of signaling state of the serial bus, and a processor configured to detect an indicator of an error signaling window in signaling state of two wires of the serial bus, the indicator of the error signaling window corresponding to a prohibited combination of symbols or a delay in control signaling, signaling an error through the bus interface during the error signaling window when an error is detected in the sequence of symbols or in timing of the indicator of the error signaling window.

A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.

A transmission driver includes a pulse generator and a current mode logic driver. The pulse generator is configured to generate and output a first pulse signal by synchronizing at a falling edge time point of a first input signal, and generate and output a second pulse signal by synchronizing at a falling edge time point of a second input signal. The current mode logic driver is configured to output a pre-emphasis signal to which pre-emphasis technique has been applied by changing a first load resistance value and a second load resistance value based on the first pulse signal and the second pulse signal, respectively.

A clock recovery circuit may include: a data slicer configured to output data values based on an input signal, a first error block, a phase adjustment loop including: a first error slicer configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data values, a second error block configured to selectively output the first error signal in response to a second pattern in the output data values, and a voltage threshold modification circuitry configured to adjust the threshold voltage based on output of the second error block, a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator.

A receiver includes an interface configured to receive a data signal based on an n-level pulse amplitude modulation (PAM-n) in which n is an integer equal to or greater than 4. The interface may include an analog-digital converting circuit configured to adjust a reference voltage, for distinguishing second bit data from the data signal in a second section, based on first bit data converted from the data signal in a first section and the first bit data converted from the data signal in the second section, the second section being after the first section.

A method and a system for processing uplink signals in cloud radio access networks are disclosed The system comprising a baseband unit and a number of remote radio heads. The baseband unit and the remote radio heads are connected through fronthaul links. When one remote radio head receives a signal transmitted from a user equipment, the remote radio head first encodes the received signal according to a post-coding matrix, then quantizes the encoded signal according to a number of quantization bits allocated to the user equipment, and finally transmits the quantized signal to the baseband unit.