A PAM4 receiver including an adaptive continuous-time linear equalizer and a method for training the same are disclosed. The PAM4 receiver and the method for training the same of the present invention employs a training pattern including a first training data pattern and second training data pattern to adaptively tune the PAM4 receiver to achieve accurate data reception and long-distance, high-speed communication.

Methods, systems are provided for reconfiguring the position of a first tap in a descrambler circuit LFSR after the LFSR has been trained and synchronized with a corresponding scrambler circuit LFSR. A data path from the second tap position to the descrambler output by-passes logic elements located in the data path from the first tap to the descrambler output, thereby reducing delay in the descrambler circuit after the reconfiguration (i.e., the “lock-shift” operation). The tap position change may be communicated by a mode manager to a corresponding scrambler circuit, for applying a matching reconfiguration in the scrambler circuit, either directly via an I/O line or indirectly. The indirect route includes in-band transmissions between two ICs with two sets of self-synchronizing scrambler/descrambler pairs, and is based on monitored receiver LFSR output signals that indicate when a scrambler/descrambler pair is synchronized or whether the output of a descrambler circuit comprises descrambled data.

A method of reducing bit error rate in a PAM4 clock data recovery circuit is described. The method includes determining a first target value of a slicing level, sweeping down from an upper voltage threshold to determine a first reference voltage value, and detecting a first filtered analog output associated with the first reference voltage value. The method also includes sweeping up from a lower voltage threshold to determine a second reference voltage value and detecting a second filtered analog output associated with the second reference voltage value. The first reference voltage value and the second reference voltage value are averaged to determine a calculated threshold value.

Methods are described allowing a vector signaling code to encode multi-level data without the significant alphabet size increase known to cause symbol dynamic range compression and thus increased noise susceptibility. By intentionally restricting the number of codewords used, good pin efficiency may be maintained along with improved system signal-to-noise ratio.

Methods are described allowing a vector signaling code to encode multi-level data without the significant alphabet size increase known to cause symbol dynamic range compression and thus increased noise susceptibility. By intentionally restricting the number of codewords used, good pin efficiency may be maintained along with improved system signal-to-noise ratio.

Methods, apparatus, and systems provide improved throughput on a communication link. An apparatus has a plurality of line drivers, a first wire state encoder configured to receive a first symbol in a sequence of symbols when a 3-wire link is in a first signaling state, and to define a second signaling state for the 3-wire link based on the first symbol and the first signaling state, a second wire state encoder configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the 3-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The 3-wire link transitions from the first to the second signaling state, and from the second to the third signaling state in consecutive transmission intervals.

Systems and methods for improving the efficiency of a rotational dynamic element matching (DEM) for Delta Sigma converters. In some implementations, the systems and methods are provided a for reducing intersymbol interference (ISI) of a Delta Sigma converter. A delta sigma converter architecture can include multiple I-DACs, and the output from each I-DAC can vary from the other I-DACs. Techniques are disclosed for decreasing mismatch among multiple I-DACs while improving efficiency of rotational dynamic element matching.

A transmission driver includes a pulse generator and a current mode logic driver. The pulse generator is configured to generate and output a first pulse signal by synchronizing at a falling edge time point of a first input signal, and generate and output a second pulse signal by synchronizing at a falling edge time point of a second input signal. The current mode logic driver is configured to output a pre-emphasis signal to which pre-emphasis technique has been applied by changing a first load resistance value and a second load resistance value based on the first pulse signal and the second pulse signal, respectively.

A driver circuit includes digital inputs, such as a first digital input and a second digital input. The digital inputs receive voltages at either a digital high-voltage or a digital low-voltage. The driver circuit has a clock input, an analog output, a first differential pair of transistors connected to the analog output, second differential pairs of transistors connected to the analog output, and voltage limiters connected to the clock input and the second differential pairs of transistors. The voltage limiters supply different voltages to the second differential pairs of transistors, which results in the second differential pairs of transistors providing analog signals to the analog output that are at different voltage steps at, and between, the digital high-voltage and the digital low-voltage.

A signal receiver includes a first preliminary receiver circuit suitable for receiving an input signal and generating a first preliminary reception signal based on a first reference voltage, a second preliminary receiver circuit suitable for receiving the input signal and generating a second preliminary reception signal based on a second reference voltage, a reception circuit suitable for selecting one of the first preliminary reception signal and the second preliminary reception signal in response to a voltage level of a reception signal and generating the reception signal using the selected signal, and a reference voltage generation circuit suitable for adjusting a voltage level of the first reference voltage based on a first offset and adjusting a voltage level of the second reference voltage based on a second offset.