Patent classifications
H04L25/49
Reduction and/or mitigation of spatial emissions in multi-antenna wireless communication systems for advanced networks
Facilitating the reduction and/or mitigation of spatial emissions in a multi antenna wireless communications system is provided herein. A system can comprise a memory that stores executable instructions that, when executed by a processor, facilitate performance of operations that can comprise applying a first signal linearization to a first output signal of a first power amplifier based on a determination that an adjacent channel leakage ratio of the first output signal of the first power amplifier fails to satisfy a defined output value. The operations can also comprise applying a second signal linearization to a group of output signals of a group of power amplifiers for a defined azimuth direction associated with channel frequencies of the group of output signals and applying a third signal linearization to the group of output signals for a defined elevation direction associated with the channel frequencies of the group of output signals.
Unequal spacing on multilevel signals
The present disclosure provides signal management with unequal eye spacing by: determining a dispersion slope of a channel between a transmitter and a receiver based on a temperature of the transmitter and a wavelength used by the transmitter to transmit signals over the channel; determining maximum and minimum powers for transmission over the channel; assigning a plurality of rails to a corresponding plurality of power levels, wherein amplitude differences between adjacent rails of the plurality of rails are based on the dispersion slope and produce a first eye pattern with a first Ratio of Level Mismatch (RLM) less than one; encoding, by the transmitter, data onto a conditioned signal according to the plurality of rails; and transmitting the conditioned signal over the channel, so that the conditioned signal demonstrates a second eye pattern with a second RLM greater than the first RLM when received at the receiver.
RF power amplifier performance by clipping prevention of large PAPR signals
Preventing RF signal distortion and signal error producing memory events in a Radio Frequency (RF) power amplifier (RFPA). An element, disposed prior to the Radio Frequency (RF) power amplifier (RFPA) in a signal path of a RF signal input to the RFPA, may enforce a maximum allowable amplitude in a high PAPR instantaneous high peak of the RF signal. An element may also increase or supplement a bias of the Radio Frequency (RF) power amplifier (RFPA) when a high PAPR instantaneous high peak is detected in the RF signal prior to receipt by the RFPA. Additionally, a first element operable detects when an instantaneous output voltage of the Radio Frequency (RF) power amplifier (RFPA) is below a predetermined voltage, and in response, a second element supplies additional current to prevent the output voltage of the RFPA from falling below a predetermined threshold voltage.
Electronic device and operating method of electronic device
An electronic device includes processing circuitry outputting first to third signals, delaying first to third signals to output fourth to sixth signals, generating a pulse signal based on the fourth signal, the fifth signal, and the sixth signal, detecting lengths of intervals, and adjusting at least one of a first code, a second code, and a third code based on fourth codes.
Controller and method for data communication
The controller includes a first equalizer, a first detector, a second detector, a multiplexer, a data clock generator, and a second equalizer. The first equalizer is configured to receive and equalize the input data. The first detector is configured to detect optimum phase of the input data. The optimum phase of the input data represents the input data peak. The second detector is configured to generate an envelope data according to the input data and detect peak of envelop with respect to sampling phase. The data clock generator is configured to generate the recovered data clock. The second equalizer is configured to generate the recovered data. The multiplexer is configured to generate an offset value according to the input data peak and the envelope data peak. The offset value represents the recovered data clock having an optimum sampling frequency and an optimum sampling phase.
DATA CARRIER APPARATUS, DATA CARRIER DRIVE APPARATUS, DATA COMMUNICATION SYSTEM, IMAGE FORMING APPARATUS AND REPLACEMENT UNIT FOR THE SAME
A system includes a data carrier drive apparatus and a data carrier apparatus. The data carrier apparatus includes: an unit configured to output transmission data during a first state and adjustment data during a second state; and a current changer configured to change a current value of a current flowing from the data carrier drive apparatus to the data carrier apparatus according to data values of the transmission data and the adjustment data. The data carrier drive apparatus includes: a detector configured to detect a detection value corresponding to the current value of the current; a determiner configured to determine the data value of the transmission data by comparing the detection value with a threshold value during the first state; and an updater configured to update the threshold value based on the detection value during the second state.
POSTAMBLE FOR MULTI-LEVEL SIGNAL MODULATION
Methods, systems, and devices for postamble for multi-level signal modulation are described. One or more channels of a bus may be driven with a multi-level signal having at least two (2) distinct signal levels. After driving the bus with the multi-level signal, at least one (1) of the channels may be terminated. In some examples, the channel may be terminated to a relatively high signal level. Before termination, the channel may be driven with a postamble having an intermediate signal level. Driving the channel to an intermediate signal level before terminating the channel (e.g., to a high signal level) may avoid maximum transitions of the signal. For example, transitions between a lowest potential signal level and the high signal level (e.g., the termination level) may be avoided.
High-speed communication link with self-aligned scrambling
High-speed communication links with self-aligned scrambling on a communication link that sends scrambled signals may include a slave device that may self-align by initially detecting an unscrambled preamble symbol and more particularly detect an edge of the unscrambled preamble symbol. Based on the detected edge, a fine alignment adjustment may be made by testing subsequent scrambled data for a repeated pattern such as an IDLE symbol by comparing the repeated pattern to a candidate scrambled sequence that has been received through the communication link. The comparison may use an exclusive OR (XOR) circuit on some bits to derive a scrambler seed that is used to test for a match for the remaining bits. If there is a match, the scrambler seed and frame alignment have been detected and alignment is achieved.
High-speed communication link with self-aligned scrambling
High-speed communication links with self-aligned scrambling on a communication link that sends scrambled signals may include a slave device that may self-align by initially detecting an unscrambled preamble symbol and more particularly detect an edge of the unscrambled preamble symbol. Based on the detected edge, a fine alignment adjustment may be made by testing subsequent scrambled data for a repeated pattern such as an IDLE symbol by comparing the repeated pattern to a candidate scrambled sequence that has been received through the communication link. The comparison may use an exclusive OR (XOR) circuit on some bits to derive a scrambler seed that is used to test for a match for the remaining bits. If there is a match, the scrambler seed and frame alignment have been detected and alignment is achieved.
High performance receivers for mobile industry processor interfaces (MIPI) and methods of operating same
A receiver, which is compatible with a mobile industry processor interface (MIPI) C-PHY physical layer, includes a plurality of variable-gain amplifiers responsive to respective multi-level signals (e.g., 3-level signals), and a plurality of filters having variable cutoff frequencies. The plurality of filters are responsive to respective signals generated by the plurality of amplifiers. An array of comparators is provided, which is responsive to signals generated by the plurality of filters. A jitter detection circuit is provided, which is configured to set respective gains of the plurality of variable-gain amplifiers and respective cutoff frequencies of the plurality of filters (e.g., high-pass filters), in response to signals generated by the array of comparators.