Patent classifications
H04L25/49
Low power chip-to-chip bidirectional communications
Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.
Wireless communication integrated with a motor control integrated circuit within a same chip package
A motor controller includes a package configured to interface with a power inverter for motor control; a wireless communication integrated circuit (IC) integrated within the package and configured to receive uplink wireless communication data and to process the uplink wireless communication data, and configured to transmit downlink wireless communication data; a motor controller IC integrated within the package and configured to perform a motor control function, including generating pulse width modulation (PWM) control signals for multi-phase motor control; and an intercommunication interface coupled to the wireless communication IC and the motor controller IC, the intercommunication interface including a plurality of inter-communication wires for information exchange of uplink information and downlink information between the wireless communication IC and the motor controller IC.
Systems and methods for delta-sigma digitization
A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.
Method and apparatus for sequence hopping in single carrier frequency division multiple access (SC-FDMA) communication systems
Methods and apparatuses are provided for transmitting and receiving a signal using a sequence in a wireless communication system. The method includes receiving, from a base station, information indicating whether sequence hopping is applied or not; transmitting, to the base station, the signal using a first sequence if a number of resource blocks allocated to the user equipment is less than a predetermined value; and transmitting, to the base station, the signal using a second sequence to which the sequence hopping is applied based on the received information if the number of the resource blocks allocated to the user equipment is greater than or equal to the predetermined value. The sequence hopping is performed using a pseudo-random function, and the sequence hopping is performed in a unit of a slot.
HIGH SPEED COMMUNICATIONS SYSTEM
Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.
HIGH SPEED COMMUNICATIONS SYSTEM
Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.
Multidrop data transfer
Multi-drop communications channels can have significantly deep notches in their frequency response causing a corresponding limitation of the effective data transmission rate. A special time-ordered coding method is described which results in the emitted spectrum of the data stream transmitted into the channel having a notch at the same frequency as the notch in the channel frequency response, permitting channel receivers to successfully decode the transmitted data stream. The described coding method may be applied at various multiples of the channel notch frequency to support different throughput rates, and may be combined with other coding techniques such as group or vector signaling codes.
Digital predistortion of signals
Systems, circuitries, and methods for predistorting a digital signal in a transmit chain based on a predistortion function are provided in which the function is determined based on a first digital signal or a first transmit chain state. A method includes: receiving a second digital signal that is input to the transmit chain, wherein the transmit chain is characterized by a present transmit chain state; performing a first operation on the second digital signal to generate an adapted digital signal, wherein the first operation is based on either a relationship between the first digital signal and the second digital signal, or a relationship between the first transmit chain state and the present transmit chain state; predistorting the adapted digital signal based on the predistortion function; and performing a second operation on the predistorted adapted signal, wherein the second operation corresponds to an inverse of the first operation.
MULTIPLEXING DISTINCT SIGNALS ON A SINGLE PIN OF A MEMORY DEVICE
Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.
MULTIPLEXING DISTINCT SIGNALS ON A SINGLE PIN OF A MEMORY DEVICE
Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.