Patent classifications
H04L25/49
Data Recovery Technique for Time Interleaved Receiver in Presence of Transmitter Pulse Width Distortion
This disclosure relates to a receiver comprising a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.
Line driver circuit
A line driver circuit includes a first input terminal, a second input terminal, a first input stage, a second input stage, a first output stage, and a second output stage. The first input stage includes a first input coupled to the first input terminal, and a second input coupled to the second input terminal. The second input stage includes a first input coupled to the first input terminal, and a second input coupled to the second input terminal. The first output stage includes a first input coupled to a first output terminal of the first input stage and a second input coupled to a first output terminal of the first input stage. A second output stage includes a first input coupled to a second output terminal of the first input stage and a second input coupled to a second output terminal of the first input stage.
Active ethernet cable
Accordingly, there are disclosed herein architectures and communication methods that enable mass-manufactured cables to perform robustly at per-lane PAM4 symbol rates up to 56 GBd and beyond. One illustrative cable embodiment includes conductor pairs connected between a first connector and a second connector. The first and second connectors are each adapted to fit into an Ethernet port of a corresponding host device to receive from that host device an electrical input signal conveying an inbound data stream to the cable, and to provide to that host device an electrical output signal conveying an outbound data stream from the cable. The first and second connectors each include a respective transceiver that performs clock and data recovery on the electrical input signal to extract and re-modulate the inbound data stream for transit via the conductor pairs as a respective electrical transit signal conveying a transit data stream.
Method and device for digital compensation of dynamic distortion in high-speed transmitters
A device and method of operation for digital compensation of dynamic distortion. The transmitter device includes at least a digital-to-analog converter (DAC) connected to a lookup table (LUT), a first shift register, and a second shift register. The method includes iteratively adjusting the input values via the LUT to induce changes in the DAC output that compensate for dynamic distortion, which depends on precursors, current cursors, and postcursors. More specifically, the method includes producing and capturing average output values for each possible sequence of three symbols using the shift register and LUT configuration. Then, the LUT is updated with estimated values to induce desired output values that are adjusted to eliminate clipping. These steps are performed iteratively until one or more check conditions are satisfied. This method can also be combined with techniques such as equalization, eye modulation, and amplitude scaling to introduce desirable output signal characteristics.
Method and device for digital compensation of dynamic distortion in high-speed transmitters
A device and method of operation for digital compensation of dynamic distortion. The transmitter device includes at least a digital-to-analog converter (DAC) connected to a lookup table (LUT), a first shift register, and a second shift register. The method includes iteratively adjusting the input values via the LUT to induce changes in the DAC output that compensate for dynamic distortion, which depends on precursors, current cursors, and postcursors. More specifically, the method includes producing and capturing average output values for each possible sequence of three symbols using the shift register and LUT configuration. Then, the LUT is updated with estimated values to induce desired output values that are adjusted to eliminate clipping. These steps are performed iteratively until one or more check conditions are satisfied. This method can also be combined with techniques such as equalization, eye modulation, and amplitude scaling to introduce desirable output signal characteristics.
C-PHY HALF-RATE WIRE STATE ENCODER AND DECODER
Methods, apparatus, and systems provide improved throughput on a communication link. An apparatus has a plurality of line drivers, a first wire state encoder configured to receive a first symbol in a sequence of symbols when a 3-wire link is in a first signaling state, and to define a second signaling state for the 3-wire link based on the first symbol and the first signaling state, a second wire state encoder configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the 3-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The 3-wire link transitions from the first to the second signaling state, and from the second to the third signaling state in consecutive transmission intervals.
Codebook to reduce error growth arising from channel errors
Techniques for limiting the growth of errors in decoded data words that arise from bit errors incurred during transmission. The growth of 3+ bit errors in the decoded data word is limited at the expense of a higher number of two bit errors, which are correctable using practical error correcting codes.
METHOD FOR ADJUSTING PHY IN FLEXE GROUP, RELATED DEVICE, AND STORAGE MEDIUM
Embodiments of this application provide a method. A receiving device determines that a first PHY needs to be added to a first FlexE group in a working state; performs deskew on the first PHY or each PHY in the first FlexE group based on a received data stream corresponding to the first PHY and a received data stream corresponding to each PHY in the first FlexE group, and restores a data stream corresponding to a client from a PHY in the first FlexE group; and if skew between the data stream corresponding to the first PHY and the data stream corresponding to each PHY in the first FlexE group after the deskew is performed is zero, restores a data stream corresponding to a client from a PHY in a second FlexE group. Flexibility of adjusting a PHY in a FlexE group in a working state is improved.
METHOD FOR ADJUSTING PHY IN FLEXE GROUP, RELATED DEVICE, AND STORAGE MEDIUM
Embodiments of this application provide a method. A receiving device determines that a first PHY needs to be added to a first FlexE group in a working state; performs deskew on the first PHY or each PHY in the first FlexE group based on a received data stream corresponding to the first PHY and a received data stream corresponding to each PHY in the first FlexE group, and restores a data stream corresponding to a client from a PHY in the first FlexE group; and if skew between the data stream corresponding to the first PHY and the data stream corresponding to each PHY in the first FlexE group after the deskew is performed is zero, restores a data stream corresponding to a client from a PHY in a second FlexE group. Flexibility of adjusting a PHY in a FlexE group in a working state is improved.
MEMORY DEVICE SUPPORTING A HIGH-EFFICIENT INPUT/OUTPUT INTERFACE AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICE
A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.