A radio frequency transmitter includes a digital-to-analog converter, an analog baseband processor, and a modulator. The digital-to-analog converter is configured to convert a digital frequency-converted signal into a first analog signal, where the digital frequency-converted signal is obtained by performing digital frequency conversion on a digital baseband signal based on a first frequency signal; the analog baseband processor is configured to perform filtering and gain adjustment on the first analog signal to obtain a second analog signal; and the modulator is configured to perform up conversion based on a second frequency signal and the second analog signal, to obtain a radio frequency signal, where the second frequency signal is determined based on a local frequency signal and the first frequency signal.

Methods, systems, and devices for pre-distortion of multi-level signaling are described. A device may identify two multi-level signals that are to be transmitted over two transmission lines at the same time. The device may estimate the crosstalk expected to be caused by one of the multi-level signals on the other during propagation. Based on the expected crosstalk, the device may generate a signal that compensates for the expected crosstalk. In some examples, the signal may be a combination of the first signal and a cancelation signal. In some examples, once the compensated signal has been generated, it is transmitted over its respective transmission line at the same time that the other multi-level is transmitted over its respective transmission line.

A signal receiving device may not need to consider jitter characteristics of a received signal by including a transition detecting device which receives first to third input signals having different signal levels for each unit interval, compares whether a signal level of a first differential signal, which is a differential signal between the first input signal and the second input signal among the first to third input signals, is greater than a first reference signal level to output a first comparison signal, and compares whether the signal level of the first differential signal is greater than a second reference signal level different from the first reference signal level to output a second comparison signal, and a clock data recovering device which recovers a clock signal embedded in the first to third input signals on the basis of the first and second comparison signals to output the recovery clock signal.

Embodiments herein provide a method for detecting a failure of a chip. The method includes dividing a plurality of channels of the chip into multiple channel groups, providing an input bit stream to each channel group of the multiple channel groups and monitoring whether there is a difference between an output bit stream of each channel in the channel group and the input bit stream, and determining based on the difference whether each of the multiple channel groups is an abnormal channel group. Input bit streams provided to respective channels in a same channel group are identical.

A secure training sequence (STS) is included in wireless packets communicated between electronic devices to assist with channel estimation and wireless ranging. The STS includes multiple STS segments generated based on outputs from a cryptographically secure pseudo-random number generator (CSPRNG), the STS segments being separated by guard intervals and formatted in accordance with an 802.15.4 data symbol format that uses burst position modulation (BPM) and binary phase shift keying (BPSK) to map bits from the CSPRNG to burst positions and pulse polarities for the STS symbols. Both a first electronic device, which generates the STS, and a second electronic device, which estimates a communication channel using the STS, have prior private knowledge of cryptographic keys required to generate a non-repetitive single-use pseudo-random (PR) sequence by the CSPRNG. The STS includes two burst position intervals per STS symbol and two possible burst positions within each burst position interval.

Mass-manufactured cables suitable for large communication centers may convert from differential PAM4 interface signaling to parallel single-ended NRZ transit signaling at 53.125 GBd to provide bidirectional data rates up to 800 Gbps and beyond. One illustrative cable embodiment includes: electrical conductors connected between a first connector and a second connector, each adapted to fit into an Ethernet port of a corresponding host device to receive an electrical input signal to the cable conveying an outbound data stream from the host device and to provide an electrical output signal from the cable conveying an inbound data stream to that host device. The electrical input and output signals employ differential PAM4 modulation to convey the inbound and outbound data streams. Each of the first and second connectors includes transceivers to perform clock and data recovery on the electrical input signal to extract and re-modulate the outbound data stream for transit via the electrical conductors as respective pairs of electrical transit signals employing single-ended NRZ modulation.

A method for transferring first and second encoded client clock signals over a carrier clock domain between integrated circuits, including in a first integrated circuit encoding a phase change of the first client clock signal from a last recorded phase onto the carrier clock signal in first bit positions, encoding a phase change of the second client clock signal from a last recorded phase onto the carrier clock signal in second bit positions different from the first bit positions, and transmitting the carrier clock signal with the encoded phases of the first client clock signal and the second client clock signal over a single wire from the first integrated circuit to a second integrated circuit.

System and method for identifying an RF emitter include: channelizers for channelizing RF signals into several channels; a compressive sensing (CS) encoder for each channel to CS encode the channelized signal to produce an encoded channelized signal in each of the plurality of channels; a summer to sum the encoded channelized signals of all of the plurality of channels to produce an I/Q data; a channelized pulse detection circuit to detect pulses in each channel and produce encoded pulse snippets from the I/Q data; a CS decoder for each channel to CS decode the encoded pulse snippets; a first machine learning device to characterize the decoded pulse snippets and to produce pulse description words (PDWs); and a second machine learning device to associate the PDWs with one or more RF emitters and identify the one or more RF emitters.

A pulse-width modulation (PWM) output stage includes a data source configured to generate a data signal; and a pulse-width modulator configured to sample the data signal at a plurality of sampling times and generate a PWM signal based on a plurality of data samples corresponding to the plurality of sampling times. The PWM signal includes a PWM cycle having a first phase of a first duration and a second phase of a second duration. The pulse-width modulator is configured to sample a first data sample at a first sampling time prior to the first phase, set the first duration and the second duration of the PWM cycle based on the first data sample, sample a second data sample at a second sampling time during the second phase, and adjust the second duration of the first PWM cycle based on the second data sample.

A signal analysis method is described. The signal analysis method includes the following steps. A first difference quantity is determined based on a first set of samples by a first polyphase filter, wherein the first set of samples includes at least two input samples. A second difference quantity is determined based on a second set of samples by a second polyphase filter, wherein the second set of samples includes at least two input samples, wherein the input samples associated with the second set of samples are time-shifted with respect to the input samples associated with the first set of samples. The first difference quantity and the second difference quantity are compared based on a predefined criterion. At least one timing parameter of the symbol sequence is determined based on the comparison of the first difference quantity and the second difference quantity. Further, a signal processing module is described.