A galvanic isolation circuit comprising: a galvanic isolator having a first side and a second side; a first communication link connected to the first side of the galvanic isolator and connectable to a first transceiver a second communication link connected to the second side of the galvanic isolator and connectable to a second transceiver; a first reference terminal connectable to the first transceiver; a second reference terminal connectable to the second transceiver; and an AC short capacitor connected between the first reference terminal and the second reference terminal.

To enable preferable signal transmission between a plurality of daisy-chained devices at low cost. A transmission device generates a plurality of signals having different voltage levels and outputs the signals to a communication line at different timings. For example, the plurality of signals having different voltage levels is generated by a plurality of drivers or one driver. A receiving side can immediately determine whether or not it is information to be passed to the subsequent stage on the basis of only a difference in voltage level without logically analyzing contents of a signal, and cost of components such as a memory, verification cost, or the like are unnecessary so that the cost can be reduced.

An electronic device includes processing circuitry outputting first to third signals, delaying first to third signals to output fourth to sixth signals, generating a pulse signal based on the fourth signal, the fifth signal, and the sixth signal, detecting lengths of intervals, and adjusting at least one of a first code, a second code, and a third code based on fourth codes.

Disclosed herein are systems and techniques for audio and lighting control in a bus system. For example, in some embodiments, a bus system may be configured for operation as a light organ and/or to generate sound effects based on accelerometer data.

Various approaches to implementing digital loopback in a radio frequency (RF) system are disclosed. An example RF system includes a receiver that includes an ADC and a transmitter that includes a DAC. The apparatus includes multiple digital loopback circuits provided at different points between the digital domain processing of the receiver and the transmitter. Each digital loopback circuit may include a combiner and one or more weighing circuits, which make the circuit programmable. The combiner of a given digital loopback circuit is configured to combine a RX signal and a TX signal at a particular point of the digital domain processing of the receiver and the transmitter where said digital loopback circuit is implemented. The one or more weighting circuits are configured to define the how much of the TX signal and/or RX signal is used for said combination.

Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.

Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.

Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.

Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.

A method for improving timing between solid state devices, e.g., in non-volatile memory device is described and includes generating timing signals from the data stream so that the data stream is free from synchronization bits. The PWM data stream is converted from CML to CMOS level. An even decoder decodes the even data signal. An odd decoder decodes the odd signal. The decoders rely on the respective signal, even or odd, to increase past a slower rising signal based on both the odd and even signals to change from a default low state to a high state. The clock signal is derived from edges of the data itself.