According to an embodiment of the disclosure, a base station communicating by using a plurality of antennas includes: a memory; a transceiver including the plurality of antennas forming an array structure; and at least one processor configured to convert first in-phase quadrature (IQ) data included in a first digital signal into radio frequency (RF) signals and then apply the RF signals to the plurality of antennas, respectively, detect a back-lobe signal beam-formed by the plurality of antennas, and perform linearization on second IQ data included in a second digital signal, based on the detected back-lobe signal.

In the conventional semiconductor device, the power consumed in ternary serial data communication cannot be reduced. According to one embodiment, the semiconductor device has a the transmission processing circuit 10 that converts the binary representation of binary Transmitted data Dbin_TX to a ternary transmitted data Dter_TX represented as a ternary number and generates a transmitted signal corresponding to this ternary Transmitted data Dter_TX, wherein the transmission processing circuit 10 verifies the frequency of occurrence of the values included in the ternary transmitted data Dter_TX, assigns the signal change pattern with the highest state transition to the transmitted signal logical level corresponding to the lowest occurrence value, and generates a transmitted signal.

A packet position modulation system includes a node configured to transmit a plurality of packets at corresponding time intervals. The node is configured to adjust, for at least one packet of the plurality of packets, the corresponding time interval to transmit the at least one packet. The system includes a base station configured to receive the plurality of packets from the node at corresponding time intervals, determine a difference between a previous time that a previous packet of the plurality of packets was received and a present time that a present packet of the plurality of packets was received, and recover coded data from the present packet based on the difference.

Systems, methods, and apparatus for transmitting additional information over a synchronous serial bus are described. A method performed at a transmitting device coupled to the serial bus includes providing first data in a data signal to be transmitted on a first wire of a multi-wire serial bus, providing a series of pulses in a clock signal to be transmitted on a second wire of a multi-wire serial bus, where each pulse has a rising edge and a falling edge, each edge being aligned with a different bit of the first data. The method may include encoding second data in the clock signal by controlling a duration of each pulse in the series of pulses based on a value of one or more bits of the second data, and transmitting the data signal and the clock signal over the serial bus.

A system and method for calibrating a pulse width modulation (PWM) signal that extends the on time by a higher resolution increment. The system comprises a PWM generator that receives a VDDIO rail to generate first and second PWM signals, the second PWM signal having an on time extended by the higher resolution increment having a commanded length. The system further comprises a VDDIO circuit that receives the VDDIO rail and outputs a VDDIO signal. First and second analog-to-digital converters are configured to generate a first and second sets of PWM samples and first and second sets of VDDIO samples. A microcontroller is configured to calculate an actual increment length based on the samples, and to compensate for a difference between the commanded length and the actual increment length.

A method of recovering information encoded by a modulated sinusoidal waveform having first, second, third and fourth data notches at respective phase angles, where a power of the modulated sinusoidal waveform is reduced relative to a power of an unmodulated sinusoidal waveform within selected ones of the first, second, third and fourth data notches so as to encode input digital data. The method includes receiving the modulated sinusoidal waveform and generating digital values representing the modulated sinusoidal waveform. A digital representation of the unmodulated sinusoidal waveform is subtracted from the digital values in order to generate a received digital data sequence, which includes digital data notch values representative of the amplitude of the modulated sinusoidal waveform within the first, second, third and fourth data notches. The input digital data is then estimated based upon the digital data notch values.

There are an amplifier circuit which includes a first current source that is connected to a power supply line to which a first electric potential is supplied, a differential input circuit that is connected between the first current source and a first node and configured to receive a differential input signal, a second current source that is connected between a power supply line to which a second electric potential is supplied and the first node, and a load circuit that is connected between a power supply line to which the first electric potential is supplied and a second node, and an inductor circuit is further connected between the first node and the second node. Thereby, the amplifier circuit achieves both lower voltage and linearity.

Systems, methods, and circuitries are provided to perform bidirectional communication using edge timing in a common signal. In one example, a method includes receiving a common signal on a signal line between a device and another device. The common signal includes a series of signal periods, and each signal period includes a first edge of a first type and a second edge of a second type different from the first type. In each signal period of the series of signal periods: information being communicated by the other device is determined based at least on the determined timing of the first edge and a timing for a subsequent second edge with respect to the signal period is determined based on information to be communicated to the other device. The subsequent second edge is generated at the selected timing in a subsequent signal period of the series of signal periods.

A semiconductor device including a signal generator and decoding and timing skew adjusting circuit is provided. The signal generator is configured to receive n multi-level signals having m signal levels and convert the n multi-level signals into n*(m1) single level signals having two signal levels. The decoding and timing skew adjusting circuit is configured to receive the single level signals, perform a predefined operation on the single level signals to generate an output signal, and compensate for timing skew between the n multi-level signals, using the single level signals. The n and m are natural numbers, where n>=2 and m>=3.

In a PAM-N receiver, sampler reference levels, DC offset and AFE gain may be jointly adapted to achieve optimal or near-optimal boundaries for the symbol decisions of the PAM-N signal. For reference level adaptation, the hamming distances between two consecutive data samples and their in-between edge sample are evaluated. Reference levels for symbol decisions are adjusted accordingly such that on a data transition, an edge sample has on average, equal hamming distance to its adjacent data samples. DC offset may be compensated to ensure detectable data transitions for reference level adaptation. AFE gains may be jointly adapted with sampler reference levels such that the difference between a reference level and a pre-determined target voltage is minimized.