Patent classifications
H04L25/49
PASSIVE MULTI-INPUT COMPARATOR FOR ORTHOGONAL CODES ON A MULTI-WIRE BUS
Methods and systems are described for receiving a plurality of signals via a plurality of wires of a multi-wire bus, the plurality of signals corresponding to symbols of a codeword of a vector signaling code, generating, using an interconnected resistor network connected to the plurality of wires of the multi-wire bus, a plurality of combinations of the symbols of the codeword of the vector signaling code on a plurality of output nodes, the plurality of output nodes including a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels, and generating a plurality of sub-channel outputs using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes.
ADAPTATION OF A TRANSMIT EQUALIZER USING MANAGEMENT REGISTERS
Selection of equalization coefficients to configure a communications link between a receiver in a host system and a transmitter in an optical or electrical communication module is performed by a management entity with access to management registers in the receiver and transmitter. Continuous modification of the selected equalization coefficients is enabled on the communications link after the communications link is established to handle varying operating conditions such as temperature and humidity.
PULSE WIDTH MODULATED RECEIVER SYSTEMS AND METHODS
A method for improving timing between solid state devices, e.g., in non-volatile memory device is described and includes generating timing signals from the data stream so that the data stream is free from synchronization bits. The PWM data stream is converted from CML to CMOS level. An even decoder decodes the even data signal. An odd decoder decodes the odd signal. The decoders rely on the respective signal, even or odd, to increase past a slower rising signal based on both the odd and even signals to change from a default low state to a high state. The clock signal is derived from edges of the data itself.
Reducing power needed to send signals over wires
Methods and apparatus are described. A method, implemented in a decoder, includes receiving two or more signals from an encoder over two or more respective wires. At least one of the two or more signals includes at least one code that was recoded by the encoder. The decoder receives a recoding table. The recoding table provides a mapping indicating the recoding for each code that was recoded by the encoder in the received two or more signals. The decoder decodes the two or more received signals using the received recoding table.
Reducing power needed to send signals over wires
Methods and apparatus are described. A method, implemented in a decoder, includes receiving two or more signals from an encoder over two or more respective wires. At least one of the two or more signals includes at least one code that was recoded by the encoder. The decoder receives a recoding table. The recoding table provides a mapping indicating the recoding for each code that was recoded by the encoder in the received two or more signals. The decoder decodes the two or more received signals using the received recoding table.
Service sending method and apparatus, service receiving method and apparatus, and network system
The present disclosure relates to a service sending method and apparatus, and a service receiving method and apparatus. One example service sending method includes obtaining, by a network device, a first data stream and a second data stream, and inserting the first data stream into the second data stream to generate a third data stream. The third data stream includes a first information block and a second information block, the first information block is used to carry the first data stream, the second information block is used to carry a first data stream distribution indication map, the first data stream distribution indication map is used to indicate a location of the first information block, and the second information block is identified by using a preset map block type.
Communication interface and method for operating a communication interface
The invention relates to a communication interface between a control unit and an electric load unit, particularly a load unit having a pump motor in a motor vehicle, wherein the control unit is designed as a transmitter and/or receiver, wherein the load unit is designed as a receiver and/or transmitter and wherein the communication between the transmitter and the receiver takes place via a signal line by means of a pulse-width-modulated signal. In this case, there is provision for the signal line to be connected to a constant current source and for the transmitter to be designed to modulate the flow of current through the signal line by means of pulse-width modulation. The invention further relates to a method for operating such a communication interface.
Multi-tap decision feedback equalizer (DFE) architecture with split-path summer circuits
Embodiments include apparatuses, methods, and systems including a decision feedback equalizer (DFE). The DFE includes a first summer circuit, a second summer circuit, a decision circuit, and a tap-delay line including a number of delay elements. The first summer circuit is to add together an analog signal and a first set of weighted feedback taps {h(j+1), . . . h(m)} of time delayed signals of a detected symbol to generate a first summand. The second summer circuit is to add together a second set of weighted feedback taps {h(k+1), h(n)} of time delayed signals of the detected symbol to generate a second summand. The decision circuit is to receive at least the first summand and the second summand, to generate the detected symbol based on a sum including the first summand and the second summand. Other embodiments may also be described and claimed.
Combined data and timing information
A measurement apparatus for providing digital data to a controller, including an Analog-to-Digital Converter (ADC) configured to transform an analog signal into a modulated digital data stream; an event detector configured to generate event indication data based on an event related to the analog signal or the digital data; and a communication interface configured to combine the modulated digital data stream and the event indication data into one or more communication frames, and to transmit the one or more communication frames to the controller.
DATA COMMUNICATION SYSTEM INCLUDING A HIGH-SPEED MAIN CHANNEL AND A LOW-SPEED STAND-BY CHANNEL WITH HIGH RELIABILITY
A data communication systems including a main channel that includes means for sending a signal, means for transmitting the signal and means for receiving the signal, the sending means sending signals at a known frequency. The communication system includes a stand-by channel that includes the following devices: a device for temporarily stopping the sent signal at instants known as stopping instants for a constant length of time that corresponds to the sending of a first determined number of sent signals, the stopping instants corresponding to temporal coding of a stand-by signal; a device for summing the amplitudes of the received signals, the summing being carried out on a second determined number of received signals; a device for temporally determining the instants corresponding to the minima of the summed signal, the determined instants having the same temporal coding as the stopping instants.