A method for communication includes producing an error signal by comparing a driving signal applied to a transmitter to an output signal generated by the transmitter in response to the driving signal. The error signal is decomposed into a linear component having a first memory depth and a nonlinear component having one or more polynomial orders and a second memory depth that is less than the first memory depth. First coefficients, up to the first memory depth, of a linear predistortion kernel are computed for application to the driving signal so as to compensate for the linear component of the error signal. Second coefficients for the one or more polynomial orders, up to the second memory depth, of a nonlinear predistortion kernel are computed so as to compensate for the nonlinear component of the error signal. Operation of the transmitter is optimized using the first and second coefficients.

Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

A line driver circuit includes a first input terminal, a second input terminal, a first input stage, a second input stage, a first output stage, and a second output stage. The first input stage includes a first input coupled to the first input terminal, and a second input coupled to the second input terminal. The second input stage includes a first input coupled to the first input terminal, and a second input coupled to the second input terminal. The first output stage includes a first input coupled to a first output terminal of the first input stage and a second input coupled to a first output terminal of the first input stage. A second output stage includes a first input coupled to a second output terminal of the first input stage and a second input coupled to a second output terminal of the first input stage.

Embodiments of the present disclosure provide a digital predistortion processing apparatus, where the apparatus includes an analog-to-digital conversion unit and n digital predistortion elements. The analog-to-digital conversion unit is connected to the n digital predistortion elements. Each digital predistortion element is configured to receive n input signals, perform digital predistortion processing on the n input signals, and then output n processed signals. The analog-to-digital conversion unit is configured to receive the n processed signals, perform signal extraction based on the n processed signals, and output an extracted signal, where a rate of the extracted signal is the same as a rate of each of the n processed signals. For an ultra-large-bandwidth signal, DPD correction may be performed without increasing a technical level of existing components such as an FPGA and an ADC, thereby greatly reducing implementation costs.

Embodiments of the present disclosure provide a digital predistortion processing apparatus, where the apparatus includes an analog-to-digital conversion unit and n digital predistortion elements. The analog-to-digital conversion unit is connected to the n digital predistortion elements. Each digital predistortion element is configured to receive n input signals, perform digital predistortion processing on the n input signals, and then output n processed signals. The analog-to-digital conversion unit is configured to receive the n processed signals, perform signal extraction based on the n processed signals, and output an extracted signal, where a rate of the extracted signal is the same as a rate of each of the n processed signals. For an ultra-large-bandwidth signal, DPD correction may be performed without increasing a technical level of existing components such as an FPGA and an ADC, thereby greatly reducing implementation costs.

There are included an error signal generation unit that generates an error signal for adding a burst error to each of an MSB and an LSB of the PAM4 signal in units of clock cycles, an error addition unit that performs an exclusive OR operation on the MSB and the LSB and the error signal and outputs bit strings obtained as a result of the operation, and a calculation unit that calculates the minimum number of clock cycles required for realizing a bit error rate of a desired test signal and the number of burst errors to be added to the MSB and the LSB during a period of the minimum number of the clock cycles.

A broadcast receiving apparatus is provided. The broadcast receiving apparatus includes a first cover with a circuit board arranged therein, a second cover coupled onto the first cover, and at least one dipole antenna coupled to the circuit board and including an antenna pattern arranged on an inner surface of the second cover.

A transmitter includes: a transmission circuit that outputs, via a transmission amplifier, transmission signals of a same frequency band; and a feedback circuit that feeds back, to the transmission circuit, a distortion compensation coefficient that is used to compensate for distortion of the transmission signals. The feedback circuit includes: a delay circuit that delays each of the transmission signals by a different amount of time; a combining unit that combines the delayed transmission signals to generate a combined signal; a signal conversion unit that converts a frequency of the combined signal to a different frequency using a local signal that is common among the transmission signals, and generates a demodulated digital signal from the combined signal of which the frequency has been converted; and a distortion compensation calculation unit that calculates the distortion compensation coefficient based on the demodulated digital signal.

A method of performing multiple data bus inversion (DBI) and a memory device performing the method are provided. The multiple DBI includes first through third DBI operations, wherein the first DBI operation determines whether to perform data inversion on a first data inversion group in which MN data bits of a MN data bit structure are grouped and performs the data inversion on the first data inversion group, the second DBI operation determines whether to perform data inversion on second data inversion groups formed by grouping M data bits from among the MN data bits and performs the data inversion on the second data inversion groups, and the third DBI operation determines whether to perform data inversion on third data inversion groups formed by grouping N data bits from among the MN data bits and performs the data inversion on the third data inversion groups.

A system and method for narrowband sinewave modulation. The system includes an input buffer for storing input digital data and a sub-periodic modulator for encoding the input digital data in a periodic waveform. The sub-periodic modulator encodes one or more bit values of the input digital data within each period of the periodic waveform. One or more digital-to-analog converters generate an encoded analog waveform from a digital representation of the periodic waveform wherein the encoded analog waveform is of a frequency f and a power P. The encoding is performed by the sub-periodic modulator such that any signal of frequency f resulting from the encoding is of a power P at least 50 dB less than power P, where f is offset from f by more than 25 Hz.