Embodiments are disclosed for channel estimation in a receiver of a communication system. An example method includes receiving, via a receiver of a communication system, an input signal. The example method further includes using a first event indicator embedded in an analog circuit of the receiver to slice the input signal to generate a sliced input signal and applying an offset to the input signal to generate an offsetted signal. The example method further includes using a second event indicator embedded in the analog circuit to slice the offsetted signal to generate a sliced offsetted signal. The example method further includes applying a first predefined delay to the sliced input signal and applying a second predefined delay to the sliced offsetted signal. The example method further includes generating a conditional ones signal based on the sliced input signal and the sliced offsetted signal and using the conditional ones signal to calibrate an equalizer embedded in the receiver.

The present technology relates to a transmission apparatus, a transmission method, and a filter circuit that make it possible to transmit a signal with high quality, the signal including a plurality of signals having different speeds. The transmission apparatus includes a detection unit that detects each of a plurality of signals having different speeds from an input signal. Further, the transmission apparatus includes an output control unit that controls output of an output signal including the plurality of signals, on the basis of detection results of the plurality of signals by the detection unit. The present technology can be applied to, for example, a transmission apparatus that transmits a serial signal conforming to the USB 3.0 standards or a transmission apparatus that converts the serial signal described above into a millimeter-wave signal or an optical signal and sends and receives the signal.

The present invention relates to a method for generating multi-level PRBS patterns for testing purposes, wherein the method includes the steps of providing a binary PRBS signal with a binary bit pattern sequence and mapping each bit of the binary bit pattern sequence to a symbol of a multilevel output.

Aspects of the disclosure are directed to auto-sweeping impedance-matching circuitry that matches an impedance of an RF antenna. As may be implemented in accordance with one or more embodiments, a transmitter that is configured and arranged to transmit signals to remote devices via the RF antenna, is used to communicate a plurality of test signals to the impedance-matching circuitry, with each test signal having a designated frequency and/or test signal pattern that is different than the designated frequency and/or test signal pattern of the other test signals. A characteristic of each of the test signals as passed through the impedance-matching circuitry is detected. For each of the test signals generated for the auto-sweep, the detected characteristic is compared to an expected characteristic for the test signal, and an output indicative of compliance of the impedance-matching circuitry with a design specification is generated and transmitted in response to the comparison.

Aspects of the disclosure are directed to auto-sweeping impedance-matching circuitry that matches an impedance of an RF antenna. As may be implemented in accordance with one or more embodiments, a transmitter that is configured and arranged to transmit signals to remote devices via the RF antenna, is used to communicate a plurality of test signals to the impedance-matching circuitry, with each test signal having a designated frequency and/or test signal pattern that is different than the designated frequency and/or test signal pattern of the other test signals. A characteristic of each of the test signals as passed through the impedance-matching circuitry is detected. For each of the test signals generated for the auto-sweep, the detected characteristic is compared to an expected characteristic for the test signal, and an output indicative of compliance of the impedance-matching circuitry with a design specification is generated and transmitted in response to the comparison.

A system and method for fast converging reference clock duty cycle correction for a digital to time converter (DTC) based analog fractional-N phase-locked loop (PLL) are herein disclosed. According to one embodiment, an electronic circuit includes a clock doubler, a comparator that outputs a value representing a difference between a voltage at a voltage-to-current (Gm) circuit and a reference voltage that is adjusted to compensate for an offset of the comparator, and a duty cycle calibration circuit that receives the value output from the comparator and adjusts a duty cycle of the PLL by extracting an error from the value output from the comparator and delaying a clock edge of the duty cycle according to the extracted error.

A data sampling circuit module, a data sampling method and a memory storage device are provided. The method includes: receiving a differential signal and generating an input data stream according to the differential signal; sampling a clock signal according to a plurality of turning points of the input data stream and outputting a sampling signal; and outputting a bit data stream corresponding to the input data stream according to the sampling signal.

A data sampling circuit module, a data sampling method and a memory storage device are provided. The method includes: receiving a differential signal and generating an input data stream according to the differential signal; sampling a clock signal according to a plurality of turning points of the input data stream and outputting a sampling signal; and outputting a bit data stream corresponding to the input data stream according to the sampling signal.

A communication device, an adapter device and a communication system (100) are provided. The system (100) includes: a master communication device (10) and a slave communication device (20), the master communication device (10) includes: a first external interface (130) including a first pin (131) and a second pin (132), and a signal generating module (110) electrically connected to the first pin (131); the signal generating module (110) is configured to generate X signals according to time interval corresponding to an N-bit string to be sent, in which the time interval corresponding to the N-bit string to be sent represents time interval between start times of each two adjacent signals, different time intervals corresponding to different bit strings, where N1, X1 and X is a natural number; said first external interface (130) is congured to send said X signals through the first pin (131).

An example optical receiver may have an optical receiver front-end, four slicers, and a logic block. The optical receiver front-end may include a transimpedance amplifier to convert a photodiode output signal to a voltage signal. Three of the slicers may be data slicers, and one of the slicers may be an edge slicer. The slicers may each: shift the voltage signal based on an offset voltage set for the respective slicer, determine whether the shifted voltage signal is greater than a threshold value and generate a number of comparison signals based on the determining, and generate multiple digital signals by demuxing the comparison signals. The logic block may perform PAM-4 to binary decoding based on the data signals output by the data slicers and clock-and-data-recovery based on the digital signals output by the edge slicer.