A method is disclosed for synchronization, comprising obtaining baseband signal samples of a baseband information signal having an in-phase signal sample and a quadrature signal sample, the baseband information signal having been generated by mixing a received modulated carrier signal with a local oscillator (LO) signal having an LO frequency, the modulated carrier signal being an in-phase signal and quadrature signal having a substantially uncorrelated nature and derived from different input data sets; determining an offset frequency rotation based on an estimated residual correlation between the in-phase signal samples and the quadrature signal samples; and, deriving synchronization information from the offset frequency rotation, wherein the received modulated carrier signal is a quadrature-modulated signal with arbitrary orthogonal in-phase and quadrature signal components.

This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a controlled oscillator signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and estimate a frequency based on the quantized phase values and the wraparound phase.

This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

The present disclosure discloses a local oscillator feedthrough signal correction apparatus, including a microprocessor control unit, a first digital-to-analog converter, a second digital-to-analog converter, a mixer, a local oscillator, a signal output line, a signal splitter, and a detector tube. The signal splitter is disposed in the signal output line, and the first digital-to-analog converter and the second digital-to-analog converter are configured to provide the mixer with quadrature direct current components VI and VQ used for local oscillator feedthrough signal correction. The mixer outputs a local oscillator feedthrough signal to the signal output line. The signal splitter obtains the local oscillator feedthrough signal by means of splitting, and the detector tube detects the local oscillator feedthrough signal. When a detection value of the local oscillator feedthrough signal exceeds a preset target value, the microprocessor control unit adjusts output values of the VI and the VQ to reduce local oscillator feedthrough.

A bandwidth adjusting method for a phase-locked loop (PLL) unit of a phase recovery module includes: adjusting an operating bandwidth of the PLL unit to a first bandwidth; measuring multiple first phase errors between a compensated input signal, which is generated according to an input signal and a phase compensating signal that the PLL unit generates, and a reference clock signal, and obtaining a first statistical value of the first phase errors; adjusting the operating bandwidth of the PLL unit to a second bandwidth; measuring multiple second phase differences between the compensated input signal and the reference clock signal, and obtaining a second statistical value of the second phase differences; and adjusting the operating bandwidth according to the first statistical value and the second statistical value. The first bandwidth and the second bandwidth are obtained by interpolating an upper bandwidth limit and a lower bandwidth limit.

A phase locked loop circuit that is capable of stabilizing a frequency of an input signal even in the case where the frequency is unstable is provided. The phase locked loop circuit that corrects a frequency error of an output signal from an oscillator to a predetermined target frequency; an ADC that converts the output signal to a digital signal; reference frequency output means that outputs a reference frequency signal; frequency error detection means that detects the frequency error based on the digital signal and the reference frequency signal; correction signal generation means that generates an error correction signal based on the frequency error; a DAC that converts the error correction signal to an analog signal; and a multiplier that multiplies the output signal by the analog signal to correct the frequency error of the output signal.

A method is disclosed for synchronization, comprising obtaining baseband signal samples of a baseband information signal having an in-phase signal sample and a quadrature signal sample, the baseband information signal having been generated by mixing a received modulated carrier signal with a local oscillator (LO) signal having an LO frequency, the modulated carrier signal being an in-phase signal and quadrature signal having a substantially uncorrelated nature and derived from different input data sets; determining an offset frequency rotation based on an estimated residual correlation between the in-phase signal samples and the quadrature signal samples; and, deriving synchronization information from the offset frequency rotation, wherein the received modulated carrier signal is a quadrature-modulated signal with arbitrary orthogonal in-phase and quadrature signal components.

This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and least-squares estimate a frequency based on the quantized phase values and the wraparound phase.