A receiver circuit that includes decision feedback equalizer sub-circuits, each associated with one of multiple divided clock signals. Each decision feedback equalizer sub-circuit is configured to receive Pulse Amplitude Modulation (PAM) signalling that represents a current network symbol. Each of the decision feedback equalizer sub-circuits is configured for sequential generation of an output symbol and includes a first delay block that is configured to apply a delay to the PAM signalling in order to provide delayed PAM signalling, where the first delay block is clocked by a divided clock signal that is associated with the decision feedback equalizer sub-circuit, a coefficient application block, a slicer, and a second delay block that is configured to apply a delay to a DFE-sub-circuit output symbol from the slicer in order to provide an output symbol, wherein the second delay block is clocked by the divided clock signal.