The present disclosure relates to a method that includes calculating a first frequency drift associated with an oscillator at a current temperature; based on the calculation, generating a first signal indicative of temperature compensation data; generating a second signal indicative of packet data and a modulation scheme; using the first signal, the second signal, and a first predetermined signal to generate a first tuning signal; and using the first tuning signal to tune a first capacitor array coupled to the oscillator and a second tuning signal to tune a second capacitor array coupled to the oscillator such that (i) the oscillator generates a modulated RF signal indicative of the packet data and (ii) the modulated RF signal has a second frequency drift that is less than a threshold.

Example radio frequency (RF) transmitters and associated methods are disclosed. One example RF transmitter includes an RF oscillator, a real-time clock (RTC) oscillator. and a control circuit. The control circuit is configured to determine whether a calibration of the RF oscillator is needed; electrically couple the RF oscillator to the RTC oscillator and initiate calibrating of the RF oscillator using the RTC oscillator when it is determined that the calibration is needed; and activate the RF oscillator to operate in an open-loop mode to generate an RF signal for data transmission. The calibration can be performed in a closed-loop mode before the data transmission or in an open-loop mode during the data transmission.

Embodiments described herein include a quadrature phase corrector (QPC) which includes multiple differential amplifies for correcting the phase of one or more clock signals. In one embodiment, the differential amplifiers are arranged in an input stage, cross-coupled stage, and ring stage. The input stage receives and buffers the input clock signal (or signals). The cross-coupled stage includes one or more latches that force one clock signal high and another low which causes the QPC to oscillate. The ring stage outputs four clock signals with adjusted phases relative to the input clock signals. In one example, the ring stage outputs a quadrature clock signal that includes four clock signals phase shifted by 90 degrees.

The devices and methods herein can produce a new waveform for transmission that is robust to carrier frequency offset (CFO) errors, and hence, enables implementation of low cost and low power consumption local oscillators at the Internet of Things (IoT) devices. The proposed method builds upon the existing 802.11ax OFDMA architecture, and adds block filtering to each resource unit to reduce out of band (OOB) emissions. Embodiments also define a modified Universal Filtered OFDM (UF-OFDM) technique that adds a Guard Interval (GI) to UF-OFDM, and thus, provides a GI-UF-OFDM architecture. The added GI helps prevent inter-symbol interference (ISI) at the receiver.

An oscillator drive circuit and a trim circuit are implemented inside an integrated circuit of a sensor. The drive circuit provides an oscillating drive signal at a resonant frequency to drive a movable mass of the sensor. The drive circuit includes a phase shift circuit having an input for receiving a first signal indicative of an oscillation of the movable mass and having an output. The phase shift circuit adds a phase shift component to the first signal and produces a second signal shifted in phase by the phase shift component. The trim circuit includes a first comparator for receiving the first signal, a second comparator for receiving the second signal, and a processing element. The processing element determines a phase lag between the first and second signals and produces trim code for use by the phase shift circuit, the trim code being configured to adjust the phase shift component.

Embodiments described herein include a quadrature phase corrector (QPC) which includes multiple differential amplifies for correcting the phase of one or more clock signals. In one embodiment, the differential amplifiers are arranged in an input stage, cross-coupled stage, and ring stage. The input stage receives and buffers the input clock signal (or signals). The cross-coupled stage includes one or more latches that force one clock signal high and another low which causes the QPC to oscillate. The ring stage outputs four clock signals with adjusted phases relative to the input clock signals. In one example, the ring stage outputs a quadrature clock signal that includes four clock signals phase shifted by 90 degrees.

An oscillator drive circuit and a trim circuit are implemented inside an integrated circuit of a sensor. The drive circuit provides an oscillating drive signal at a resonant frequency to drive a movable mass of the sensor. The drive circuit includes a phase shift circuit having an input for receiving a first signal indicative of an oscillation of the movable mass and having an output. The phase shift circuit adds a phase shift component to the first signal and produces a second signal shifted in phase by the phase shift component. The trim circuit includes a first comparator for receiving the first signal, a second comparator for receiving the second signal, and a processing element. The processing element determines a phase lag between the first and second signals and produces trim code for use by the phase shift circuit, the trim code being configured to adjust the phase shift component.

A digital to analog signal conversion system with a local oscillator, a control circuit, a radio-frequency digital to analog converter circuit, and a power combiner circuit is presented. The local oscillator generates a plurality of local oscillator phase signals. The control circuit receives a baseband in-phase (I) signal and a baseband quadrature (Q) signal and generates a plurality of control signals. The radio-frequency digital to analog converter circuit includes first and second pluralities of switch units that generate positive and negative radio-frequency signals respectively, based on the plurality of local oscillator phase signals and the plurality of control signals. The power combiner circuit generates a radio-frequency output signal based on a combination of the positive radio-frequency signal from the first plurality of switch units and the negative radio-frequency signal from the second plurality of switch units.