A circuit structure for efficiently demodulating an FSK signal in a wireless charging device, comprising a data sampling module, a period point counting module, a data distribution module, and a period point processing module. An input terminal of the period point counting module is connected to an output terminal of the data sampling module; an input terminal of the data distribution module is connected to an output terminal of the period point counting module; and an input terminal of the period point processing module is connected to an output terminal of the data distribution module.

Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.

Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.

An apparatus includes a first half-cell, a second half cell and a multiplexer. The first half-cell may comprise a first input stage configured to present a first input signal to a first auto-zero stage. The second half-cell may comprise a second input stage configured to present a second input signal to a second auto-zero stage. The multiplexer may receive a first output from the first auto-zero stage, receive a second output from the second auto-zero stage and present one of the first output and the second output. The first half-cell and the second half-cell may implement a capacitive coupling. The capacitive coupling may provide a rail-to-rail common-mode input range. The first half-cell and the second half-cell may prevent a mismatch between data signals and clock signals. The first half-cell and the second half-cell may each be configured to implement a calibration when idle.

A data carrier apparatus includes a duty detector configured to determine a duty ratio of each pulse of a pulse signal that is received, a frequency detector configured to determine a period of each pulse of the pulse signal, and a demodulator configured to determine a value of data being carried by the pulse signal based on a determination result of the duty detector unit and a determination result of the frequency detector.

The present invention is related to a method and apparatus for implementing space frequency block coding (SFBC) in an orthogonal frequency division multiplexing (OFDM) wireless communication system. A wireless transmit/receive unit (WTRU) including a transceiver and a processor is configured to receive, via the transceiver, an orthogonal frequency division multiplexing (OFDM) signal, wherein the OFDM signal comprises a channel coded data stream that was space frequency block coding (SFBC) encoded such that the SFBC encoding was performed using a plurality of pairs of OFDM sub-carriers. The processor is further configured to decode the OFDM signal.

The present invention is related to a method and apparatus for implementing space frequency block coding (SFBC) in an orthogonal frequency division multiplexing (OFDM) wireless communication system. A wireless transmit/receive unit (WTRU) including a transceiver and a processor is configured to receive, via the transceiver, an orthogonal frequency division multiplexing (OFDM) signal, wherein the OFDM signal comprises a channel coded data stream that was space frequency block coding (SFBC) encoded such that the SFBC encoding was performed using a plurality of pairs of OFDM sub-carriers. The processor is further configured to decode the OFDM signal.

A continuous-time sampler has series-connected delay lines with intermediate output taps between the delay lines. Signal from an output tap can be buffered by an optional voltage buffer for performance. A corresponding controlled switch is provided with each output tap to connect the output tap to an output of the continuous-time sampler. The delay lines store a continuous-time input signal waveform within the propagation delays. Controlling the switches corresponding to the output taps with pulses that match the propagation delays can yield a same input signal value at the output. The continuous-time sampler effectively holds or provides the input signal value at the output for further processing without requiring switched-capacitor circuits that sample the input signal value onto some capacitor. In some cases, the continuous-time sampler can be a recursively-connected delay line. The continuous-time sampler can be used as the front end sampler in a variety of analog-to-digital converters.

A transmission apparatus includes a waveform processing circuit. The waveform processing circuit is configured to receive a modulated signal indicating each of values of pulses by one of four signal levels including first, second, third, and fourth signal levels ascending in this order. The waveform processing circuit is configured to output a signal corresponding to the modulated signal. A portion of the output signal corresponding to a portion of the modulated signal that transitions between the first and fourth signal levels, transitions between a first adjusted signal level different from the first signal level and a second adjusted signal level different from the fourth signal level. The transmission apparatus is configured to transmit a signal corresponding to the signal output from the waveform processing circuit through a wired communication path.

A transmission apparatus includes a waveform processing circuit. The waveform processing circuit is configured to receive a modulated signal indicating each of values of pulses by one of four signal levels including first, second, third, and fourth signal levels ascending in this order. The waveform processing circuit is configured to output a signal corresponding to the modulated signal. A portion of the output signal corresponding to a portion of the modulated signal that transitions between the first and fourth signal levels, transitions between a first adjusted signal level different from the first signal level and a second adjusted signal level different from the fourth signal level. The transmission apparatus is configured to transmit a signal corresponding to the signal output from the waveform processing circuit through a wired communication path.