A signal demodulation apparatus and method for a closed communication system are provided. An analog voltage comparator is configured to convert a modulated signal and output the digital signal. The modulated signal is a 2ASK, 2FSK or 2PSK modulated signal. A sampling decider is configured to sample the digital signal to obtain a sampled digital signal. The sampling decider includes a high-frequency clock sampling circuit and a feature extracting and deciding circuit. The high-frequency clock sampling circuit is configured to sample the digital signal and to sample at least two points for a high level of any pulse of the digital signal. The feature extracting and deciding circuit is configured to extract a feature of the sampled digital signal to obtain an extracted feature of the sampled digital signal, and compare the extracted feature with features of known digital modulated signals to acquire a value represented by the digital signal.

Provided is a multi-source signal generator including a voltage-controlled oscillator configured to generate a first source signal having a first frequency to deliver the first source signal to a first output port, a Single Pole Double Throw (SPDT) switch configured to select the first source signal or an external source signal, a first power amplifier configured to amplify power of the first source signal selected by the SPDT switch, and a multi-source converting unit configured to multiply a frequency of the amplified first source signal or divide power of the amplified first source signal to generate multi-source signals, wherein the frequency of the first source signal and frequencies of the multi-source signals are included in a millimeter wave band or sub-terahertz (THz) band.

Provided is a multi-source signal generator including a voltage-controlled oscillator configured to generate a first source signal having a first frequency to deliver the first source signal to a first output port, a Single Pole Double Throw (SPDT) switch configured to select the first source signal or an external source signal, a first power amplifier configured to amplify power of the first source signal selected by the SPDT switch, and a multi-source converting unit configured to multiply a frequency of the amplified first source signal or divide power of the amplified first source signal to generate multi-source signals, wherein the frequency of the first source signal and frequencies of the multi-source signals are included in a millimeter wave band or sub-terahertz (THz) band.

An occurrence of a first set of n periods of a frequency-shift-keying (FSK)-modulated waveform is counted, where n is an integer number. The n periods of the FSK-modulated waveform in the first set have a first time duration. An occurrence of a second set of n periods of the waveform is counted. The n periods of the waveform in the second set have a second time duration. The first time duration is determined based on the counting of the first set of n periods. The second time duration is determined based on the counting of the second set of n periods. A difference between the first time duration and the second time duration is compared to a threshold. Changes in frequency of the waveform are detected based on the comparing of the difference between the first time duration and the second time duration to the threshold.

An occurrence of a first set of n periods of a frequency-shift-keying (FSK)-modulated waveform is counted, where n is an integer number. The n periods of the FSK-modulated waveform in the first set have a first time duration. An occurrence of a second set of n periods of the waveform is counted. The n periods of the waveform in the second set have a second time duration. The first time duration is determined based on the counting of the first set of n periods. The second time duration is determined based on the counting of the second set of n periods. A difference between the first time duration and the second time duration is compared to a threshold. Changes in frequency of the waveform are detected based on the comparing of the difference between the first time duration and the second time duration to the threshold.

A receiver for demodulating a pulse width modulated (PWM) signal, comprises: a voltage level shifter for shifting the PWM signal to predefined transistor voltage levels; a half-rate PWM decoder for receiving the shifted PWM signal; and a 2-bit-to-N-bit deserializer. The half-rate PWM decoder comprises a first decoder core, a second decoder core, a controller, and a sampler and retiming circuit. The first decoder core and the second decoder core are configured to decode alternating periods of the shifted PWM signal. The controller is coupled to the first decoder core, the second decoder core, the sampler and retiming circuit. The retiming circuit is configured to receive clock signals from the controller and to output half-rate even data from the first decoder core and half-rate odd data from the second decoder core. Outputs of the retiming circuit and an output of the controller are coupled to inputs of the deserializer.

A method allowing a receiver device of a wireless communication system to receive a useful signal emitted by an emitter device. The useful signal corresponding to a signal, the phase or frequency of which is modulated by a sequence of two-state symbols corresponding to a sequence of binary data. A temporal envelope of the useful signal is detected and compared to a preset threshold value. Transitions between consecutive useful-signal symbols are detected, on the basis of the result of the comparison. A sequence of binary data is extracted from the useful signal depending on the detected transitions.

In an embodiment of the invention there is a cyclotronic actuator utilizing a high-voltage plasma driver connected to a first electrode. A second electrode is grounded and the two are isolated from each other by a dielectric plate. A magnet is positioned beneath the dielectric plate such that a coaxial dielectric barrier discharge plasma is formed outwardly between the first electrode across the dielectric plate. The magnet positioned beneath the dielectric plate introduces a magnetic field transverse to the plasma current path, such that the plasma discharge discharges radially and the local magnetic field is oriented vertically in a direction perpendicular to the dielectric plate to create a Lorentz Force, which forces the plasma discharge to move radially outwardly in a curved radial streamer mode pattern.

An apparatus includes a first half-cell, a second half cell and a multiplexer. The first half-cell may comprise a first input stage configured to present a first input signal to a first auto-zero stage. The second half-cell may comprise a second input stage configured to present a second input signal to a second auto-zero stage. The multiplexer may receive a first output from the first auto-zero stage, receive a second output from the second auto-zero stage and present one of the first output and the second output. The first half-cell and the second half-cell may implement a capacitive coupling. The capacitive coupling may provide a rail-to-rail common-mode input range. The first half-cell and the second half-cell may prevent a mismatch between data signals and clock signals. The first half-cell and the second half-cell may each be configured to implement a calibration when idle.

A receiver for demodulating a pulse width modulated (PWM) signal, comprises: a voltage level shifter for shifting the PWM signal to predefined transistor voltage levels; a half-rate PWM decoder for receiving the shifted PWM signal; and a 2-bit-to-N-bit deserializer. The half-rate PWM decoder comprises a first decoder core, a second decoder core, a controller, and a sampler and retiming circuit. The first decoder core and the second decoder core are configured to decode alternating periods of the shifted PWM signal. The controller is coupled to the first decoder core, the second decoder core, the sampler and retiming circuit. The retiming circuit is configured to receive clock signals from the controller and to output half-rate even data from the first decoder core and half-rate odd data from the second decoder core. Outputs of the retiming circuit and an output of the controller are coupled to inputs of the deserializer.