A digital signal processor which performs digital signal processing of a digital signal includes a statistical analysis method which calculates a moving average and a standard deviation from the digital signal, performs statistical decision deciding whether or not the digital signal is within a predetermined range obtained from the moving average and the standard deviation, and corrects the digital signal outside the range within the range. Statistical analysis of the digital signal is performed, thereby suppressing transient changes without increasing the number of times of averaging during the digital signal processing.

A digital signal processor which performs digital signal processing of a digital signal includes a statistical analysis method which calculates a moving average and a standard deviation from the digital signal, performs statistical decision deciding whether or not the digital signal is within a predetermined range obtained from the moving average and the standard deviation, and corrects the digital signal outside the range within the range. Statistical analysis of the digital signal is performed, thereby suppressing transient changes without increasing the number of times of averaging during the digital signal processing.

The present technology relates to a signal processing apparatus and method which can suppress increase in power consumption.

In an aspect of the present technology, control data, which is for controlling frequency modulation to a carrier signal using digital data to be transmitted, and for suppressing a time average of a fluctuation amount of a frequency modulation amount more than a case of controlling the frequency modulation to the carrier signal using the digital data is generated, the frequency modulation is performed to the carrier signal on the basis of the generated control data, and the carrier signal to which the frequency modulation is performed is transmitted as a transmission signal. The present technology can be applied to, for example, a signal processing apparatus, a transmission apparatus, a reception apparatus, a communication apparatus, or an electronic apparatus having a transmission function, a reception function, or a communication function, or a computer which controls these.

The present technology relates to a signal processing apparatus and method which can suppress increase in power consumption.

In an aspect of the present technology, control data, which is for controlling frequency modulation to a carrier signal using digital data to be transmitted, and for suppressing a time average of a fluctuation amount of a frequency modulation amount more than a case of controlling the frequency modulation to the carrier signal using the digital data is generated, the frequency modulation is performed to the carrier signal on the basis of the generated control data, and the carrier signal to which the frequency modulation is performed is transmitted as a transmission signal. The present technology can be applied to, for example, a signal processing apparatus, a transmission apparatus, a reception apparatus, a communication apparatus, or an electronic apparatus having a transmission function, a reception function, or a communication function, or a computer which controls these.

A digital television (DTV) receiving system includes an information detector, a resampler, a timing recovery unit, and a carrier recovery unit. The information detector detects a known data sequence which is periodically inserted in a digital television (DTV) signal received from a DTV transmitting system. The resampler resamples the DTV signal at a predetermined resampling rate. The timing recovery unit performs timing recovery on the DTV signal by detecting a timing error from the resampled DTV signal using the detected known data sequence. The carrier recovery unit performs carrier recovery on the resampled DTV signal by estimating a frequency offset value of the resampled DTV signal using the detected known data sequence.

Embodiments provide a data receiver, the data receiver being configured to receive a signal including a sequence of N bits so as to obtain a reception signal, wherein N is a natural number greater than or equal to eight, N≥8, wherein the data receiver is configured to sample the reception signal with a sampling rate that corresponds, with an intentional deviation of up to 2/N, to one sample value per bit of the sequence of N bits so as to obtain a sequence of received bits, wherein the data receiver is configured to correlate the sequence of received bits with K different sequences of N-1 reference bits so as to obtain K partial correlation results, wherein K is smaller than or equal to N-1 and greater than or equal to three, N-1≥K≥3.

A DARC signal demodulation circuit assemblage for recovering a DARC signal (DARC data) from an FM multiplex transmission signal includes: a pilot tone regulation circuit to obtain first and second mutually orthogonal oscillation synchronous with a stereo pilot tone encompassed by the FM multiplex transmission signal; a frequency quadruplication section for obtaining third and fourth mutually orthogonal oscillation having a frequency quadrupled as to the stereo pilot tone; a first multiplication section for obtaining a first multiplication signal from the FM multiplex transmission signal and from the third oscillation; a second multiplication section for obtaining a second multiplication signal from the FM multiplex transmission signal and from the fourth oscillation; first/second low-pass filters for obtaining first/second DARC signal components by low-pass filtration of the first and second multiplication signals; and an FM demodulation section for obtaining the DARC signal from a frequency demodulation of the first/second DARC signal components.

A DARC signal demodulation circuit assemblage for recovering a DARC signal (DARC data) from an FM multiplex transmission signal includes: a pilot tone regulation circuit to obtain first and second mutually orthogonal oscillation synchronous with a stereo pilot tone encompassed by the FM multiplex transmission signal; a frequency quadruplication section for obtaining third and fourth mutually orthogonal oscillation having a frequency quadrupled as to the stereo pilot tone; a first multiplication section for obtaining a first multiplication signal from the FM multiplex transmission signal and from the third oscillation; a second multiplication section for obtaining a second multiplication signal from the FM multiplex transmission signal and from the fourth oscillation; first/second low-pass filters for obtaining first/second DARC signal components by low-pass filtration of the first and second multiplication signals; and an FM demodulation section for obtaining the DARC signal from a frequency demodulation of the first/second DARC signal components.

A system and method involve receiving, at a processor, a phase modulated signal such as an optical or electromagnetic signal, using one or more samples of an in-phase component I(t) and a quadrature component Q(t) of the received phase modulated signal to generate, at the processor, a processed signal using the equation [A−B×I(t)]×Q(t), where A and B are numerical parameters, and inputting the processed signal into a receiver operatively connected to the processor. The processed signal may be filtered prior to being input into the receiver. Parameters A and B may be selected to vary complexity and performance of the receiver while controlling distortion for different modulation indices.

Embodiments of the present invention provide a carrier synchronization method, circuit, and system. The method includes performing n times frequency multiplication on a received signal; performing narrowband filtering at least twice and rectangular wave shaping at least twice on the signal obtained after the n times frequency multiplication; and performing n times frequency division on the signal obtained after the filtering and shaping, to restore a carrier signal. The variable n is a positive integer greater than or equal to 4.