The present application provides a non-orthogonal demodulation module, receiving a received signal and the received signal is related to a summation of a plurality of transmitted signals. The plurality of transmitted signals are corresponding to a plurality of frequencies, and the plurality of transmitted signals are not orthogonal to each other. The non-orthogonal demodulation module comprises a mixing-and-integrating unit, configured to perform mixing operations and integrating operations on the received signal respectively at the plurality of frequencies, to generate a plurality of in-phase components and a plurality of quadrature components corresponding to the plurality of frequencies; and a decoding unit, configured to generate at least a decoding matrix, and compute a plurality of energies corresponding to the plurality of transmitted signals according to the at least a decoding matrix, the plurality of in-phase components and the plurality of quadrature components.

A radio receiver device is arranged to receive a radio signal modulated with a data packet including an address portion. The radio receiver comprises: a synchronisation circuit portion arranged to produce synchronization information corresponding to the data packet; a demodulation circuit portion comprising a correlator, wherein said demodulation circuit portion is arranged to receive the radio signal and to produce an estimate of the address portion comprising a plurality of demodulated bits using said correlator and the synchronisation information; an address checking circuit portion arranged to receive the plurality of demodulated bits, to check said plurality of demodulated bits for a predetermined bit pattern, and to produce a match flag if it determines that the plurality of demodulated bits corresponds to the predetermined bit pattern. The radio receiver device is arranged such that, upon detecting an upcoming timeout event, the demodulation circuit portion sends a timeout warning signal to the address checking circuit portion using a handshaking channel therebetween; said address checking circuit portion being arranged such that, if it receives the timeout warning signal, it stops checking the plurality of demodulated bits for the predetermined bit pattern.

A communication system comprises a transmitter and a receiver that communicate differential phase modulated data over a wireline channel pair. The transmitter encodes data symbols by generating first and second data signals with differentially phase shifted signal transitions with respect to one another. The receiver receives the first data signal and the second data signal and samples the first data signal based on a signal transition timing of the second data signal to generate a first output data symbol. The receiver furthermore samples the second data signal based on signal transition timing of the first data signal to generate a second output data symbol.

A digital radio receiver has a matched filter bank of filter modules for receiving phase- or frequency-modulated radio signals. Each module cross-correlates a sampled signal with a respective multi-symbol filter sequence, using a plurality of samples in each symbol period. The matched filter bank calculates first values (z.sub.n(1)), for respective symbol periods, of a cross-correlation of the sampled signal with a first complex exponential function defined at sample points over one symbol period, and calculates second values (z.sub.n(1)), for the respective symbol periods, of a cross-correlation of the sampled signal with a second, different, complex exponential function. A set of the filter modules cross-correlates the sampled signal with their respective filter sequences using an algorithm that takes, as input, the first values (z.sub.n(1)) for symbol periods at which the respective filter sequence has a first value, and the second values (z.sub.n(1)) for symbol periods at which the filter sequence has a second, different, value.

The present invention relates to a system for demodulating or blind searching the characteristics of digital telecommunication signals, characterized in that it comprises at least one hardware architecture or hardware and firmware comprising memories and one or more processing units for implementing a network of specific computation blocks connected together, including a first specialized block of the network estimating at least one filter for acquiring the blind signal, and a second block subsequently producing at least one module for estimating the amplification of the observed signals in order to subsequently assess the other characteristics of the signals observed by the other computation blocks of the network, at least a third specialized computation block producing a decision-making module for computing an error signal and back-propagating the computed errors to each of the preceding residual blocks (propagate, update).

The present invention concerns a real-time method for the blind demodulation of digital telecommunication signals, based on the observation of a sampled version of this signal. The method comprises the following steps: acquisition, by a sampling, of a first plurality of signals in order to each constitute an input of a network of L processing blocks (G, F, H), also referred to here as specialized neurons, each neuron being simulated by the outputs of the preceding block, the first plurality of signals being input into the first block simulating a first neuron of the network in order to generate a plurality of outputs of the first block; each neuron F being simulated by the outputs of an upstream chain G and stimulating a downstream chain H; each set of samples passes through the same processing chain; the outputs of the last blocks of the network ideally correspond to the demodulated symbols; addition of a nonlinearity to each of the outputs of the last block of the network making it possible to calculate an error signal and propagation of this error in the reverse direction of the processing chain (retropropagation); estimation, upon receipt of the error by each neuron (i), of a corrective term .sub.i and updating, in each block, of the value of the parameter .sub.i according to .sub.i+=.sub.i.

A method is disclosed of generating a frequency shift keying (FSK) signal comprised in an orthogonal frequency division multiplexing (OFDM) signal comprising a plurality of sub-carriers. The FSK signal comprises FSK symbols wherein each FSK symbol has a corresponding FSK symbol frequency. The method comprises assigning a set of adjacent sub-carriers to transmission of the FSK signal (wherein the set is a sub-set of the plurality of sub-carriers), and associating each FSK symbol frequency with a corresponding sub-carrier in the set of adjacent sub-carriers. The method also comprises selecting, for each FSK symbol to be transmitted, an FSK symbol phase such that an FSK signal phase at a start of the FSK symbol to be transmitted meets a phase difference criterion in relation to the FSK signal phase at an end of an immediately previous FSK symbol. The method further comprises generating the FSK signal comprising the FSK symbol to be transmitted by modulating the sub-carrier corresponding to the FSK symbol frequency based on the selected FSK symbol phase and muting the remaining sub-carriers of the set. Corresponding arrangement, access point and computer program product are also disclosed.

A method of demodulating a signal that is phase modulated to convey R chips having phase transitions between adjacent ones of the R chips to represent chip states, and an overlay symbol spanning the R chips, wherein R>1, and wherein the phase transitions are rotated in a same direction according to an overlay symbol state, comprises: first processing the signal including: accumulating a respective phase of each chip into a respective first chip magnitude, to produce R first chip magnitudes; and accumulating the R first chip magnitudes to produce a first magnitude; second processing the signal including: accumulating a respective phase of each chip into a respective second chip magnitude, to produce R second chip magnitudes; and accumulating the R second chip magnitudes to produce a second magnitude; and determining the overlay symbol state based on the first magnitude and the second magnitude.

A communication system comprising: input buffers adapted for buffering incoming data streams of samples from one or more channels; a receiver adapted for sequentially processing data from the input buffers; a processing rate of the receiver is higher than or equal to an incoming data rate of the incoming data; context memory adapted for saving an internal status of the receiver after processing the data corresponding with an input buffer before switching to a next input buffer and for restoring the internal status, wherein the receiver is adapted for processing the incoming data in a frame detection phase, and in a frame demodulation phase in which frames and/or subframes are demodulated into bits and wherein the internal status of the receiver related to an input buffer is only saved and restored in the frame detection phase or before and after demodulating subframes.

A communication system comprising: input buffers adapted for buffering incoming data streams of samples from one or more channels; a receiver adapted for sequentially processing data from the input buffers; a processing rate of the receiver is higher than or equal to an incoming data rate of the incoming data; context memory adapted for saving an internal status of the receiver after processing the data corresponding with an input buffer before switching to a next input buffer and for restoring the internal status, wherein the receiver is adapted for processing the incoming data in a frame detection phase, and in a frame demodulation phase in which frames and/or subframes are demodulated into bits and wherein the internal status of the receiver related to an input buffer is only saved and restored in the frame detection phase or before and after demodulating subframes.