A signal specification identification apparatus includes processing circuitry that estimates the transmission rate of a received signal, performs sampling frequency conversion on the received signal, calculates a probability corresponding to each of a plurality of candidates for a specification of the received signal, selects a candidate using the respective probabilities, and calculates reliability corresponding to a selected candidate, determines whether to output the selected candidate as an identification result or perform the sampling frequency conversion again, based on the reliability, and changes a parameter indicating the ratio of the sampling frequency conversion when it is determined that the sampling frequency conversion is to be performed again. Processing is repeated until the processing circuitry determines that the selected candidate as the identification result is to be output.

Various embodiments provide for data transmission using modulated carrier signals to carry data, where the carrier signal comprises a predetermined sequence of symbols. An embodiment can be used in such applications as data network communications between sensors (e.g., cameras, motion, radar, etc.) and computing equipment within vehicles (e.g., smart and autonomous cars).

A method to generate a wireless waveform for use in a wireless communication system, a wireless communication system and computer program product thereof

The method comprises the generation of a waveform for application in the wireless communication system characterized by significant phase noise, Doppler spread, multipath, frequency instability, and/or low power efficiency by at the transmitter side: creating a discrete-time instantaneous frequency signal {tilde over (f)}[n]; appending a cyclic prefix with length L.sub.CP to the beginning of the discrete-time instantaneous frequency signal {tilde over (f)}[n]; constructing a discrete-time unwrapped instantaneous phase φ[n]; constructing a discrete-time complex baseband signal, and appending at the beginning a Constant Amplitude Zero Autocorrelation, CAZAC, signal of length L.sub.CP for multipath detection; and passing the constructed discrete-time complex baseband signal through a digital-to-analog, DAC, converter to yield the continuous-time radio frequency signal s(t) after conversion to the carrier frequency.

A method to generate a wireless waveform for use in a wireless communication system, a wireless communication system and computer program product thereof

The method comprises the generation of a waveform for application in the wireless communication system characterized by significant phase noise, Doppler spread, multipath, frequency instability, and/or low power efficiency by at the transmitter side: creating a discrete-time instantaneous frequency signal {tilde over (f)}[n]; appending a cyclic prefix with length L.sub.CP to the beginning of the discrete-time instantaneous frequency signal {tilde over (f)}[n]; constructing a discrete-time unwrapped instantaneous phase φ[n]; constructing a discrete-time complex baseband signal, and appending at the beginning a Constant Amplitude Zero Autocorrelation, CAZAC, signal of length L.sub.CP for multipath detection; and passing the constructed discrete-time complex baseband signal through a digital-to-analog, DAC, converter to yield the continuous-time radio frequency signal s(t) after conversion to the carrier frequency.

A system and module for, and a method of correcting, memory misalignment in a phase shift keying receiver is disclosed. Embodiments include a system having: an analog front end for receiving a demodulated signal having a preamble portion, and for generating a digital register input signal including a received preamble portion; a finite state machine for selecting a memory address of the demodulated signal based on the received preamble portion; a preamble memory for storing all possible preambles contained within the demodulated signal and for supplying a selected preamble memory output corresponding to the selected memory address; and a memory alignment module configured to compare phase information of symbols of the preamble portion and preamble phase information of symbols of the selected preamble memory output. This system checks that the preamble portion of the register input signal aligns with the selected preamble memory output and makes corrections when necessary.

A BPSK demodulator circuit comprises: a sideband-separating and lower sideband signal-delaying unit which separates a modulated signal into a lower sideband and an upper sideband by a primary low pass filter and a primary high pass filter having a cut-off frequency as a carrier frequency, and which outputs an upper sideband analog signal and an analog signal delayed by ¼ of a cycle of the carrier frequency from a lower sideband analog signal; a data demodulating unit which demodulates digital data by means of latching, through a hysteresis circuit, an analog pulse signal appearing in accordance with the phase change part of a signal generated by the sum of the analog signals; and a data clock restoring unit which generates a data clock by using a data signal and a signal having the delayed lower sideband analog signal digitized through a comparator.

A BPSK demodulator circuit comprises: a sideband-separating and lower sideband signal-delaying unit which separates a modulated signal into a lower sideband and an upper sideband by a primary low pass filter and a primary high pass filter having a cut-off frequency as a carrier frequency, and which outputs an upper sideband analog signal and an analog signal delayed by ¼ of a cycle of the carrier frequency from a lower sideband analog signal; a data demodulating unit which demodulates digital data by means of latching, through a hysteresis circuit, an analog pulse signal appearing in accordance with the phase change part of a signal generated by the sum of the analog signals; and a data clock restoring unit which generates a data clock by using a data signal and a signal having the delayed lower sideband analog signal digitized through a comparator.

An interference cancellation (IC) processor, a method, a method of manufacturing a semiconductor device, and a method of constructing an integrated circuit are provided. The IC processor includes a plurality of mono interference cancellation (MIC) filter estimation processors; a combined effective channel calculation processor; a combined filter calculation processor; and a combined filter processor, including a first input connected to the output of the combined filter calculation processor, a second input for receiving a signal for setting a length of the combined filter that is connected to a second input of the IC processor, a third input connected to the input of the MIC-BRC processor, and an output for providing a filtered output of a de-rotated GMSK signal that is connected to a second output of the IC processor that provides a filtered output y.sub.i of the de-rotated GMSK signal.

In accordance with an embodiment, a device configured to detect a presence of at least one digital pattern within a signal includes J memory circuits having respectively Nj memory locations; and processing circuitry comprising an accumulator configured to successively address the memory locations of the J memory circuits in a circular manner at frequency F and during an acquisition time, and successively accumulate and store values indicative of a signal intensity in parallel in the J addressed memory locations of the J memory circuits, and a detector configured to detect the possible presence of the at least one pattern.

In one example, an apparatus includes an offset tunable edge slicer having an input to receive a pulse amplitude modulation signal. The offset tunable edge slicer also has a plurality of possible offset settings corresponding to a plurality of different reference voltages of the offset tunable edge slicer. A multiplexer has an output coupled to the input of the offset tunable edge slicer and an input to receive a control signal that selects one of the plurality of possible offset settings for the offset tunable edge slicer. A phase detector has an input coupled to an output of the offset tunable edge slicer.