H04L45/74591

System and method for using subnet prefix values in global route header (GRH) for linear forwarding table (LFT) lookup in a high performance computing environment

System and method for supporting intra- and inter-subnet address resolution in a network environment using the same linear forwarding tale (LFT) for both the intra- and inter-subnet forwarding. Subnet prefix values in global route headers (GRHs) are used for linear forwarding table (LFT) lookup in a high performance computing environments. An exemplary can provide for use of an Inter Subnet Route Number (ISRN) embedded in the subnet prefix values in the GRHs for LFT lookup in a network switch environment in a high performance computing environment such as a network having an InfiniBand (IB) architecture. A method can provide, at a computer environment, including a network fabric, one or more subnets, each of which subnets are associated with one or more network switches or hosts. The system and method is compatible with legacy switches and nodes that are not conversant with the ISRNs.

Flowlet scheduler for multicore network processors
10862617 · 2020-12-08 · ·

Systems and methods of using a packet order work (POW) scheduler to assign packets to a set of scheduler queues for supplying packets to parallel processing units. A processing unit and the associated scheduler queue is dedicated to a specific flow until a queue-reallocation event, which may correspond to the associated scheduler queue being idle for at least a certain interval as indicated by its age counter, or the queue being the LRU, when a new flow arrives. In this case, the scheduler queue and the associated processing unit may be reallocated to the new flow and disassociated with the previous flow. As a result, dynamic packet workload balancing can be advantageously achieved across the multiple processing paths.

Systems and methods for frame lookup and forwarding in a network

A network device includes a plurality of ports, a lookup circuit, and a traffic control circuit. The lookup circuit is configured to provide a first action for a first frame to be forwarded using a first forwarding path between a first set of two ports of the plurality of ports. The lookup circuit is further configured to and provide a second action for a second frame to be forwarded using a second forwarding path between a second set of two ports of the plurality of ports. The traffic control circuit configured to forward the first frame based on the first action and forward the second frame based on the second action.

Systems and methods for intelligent routing and content placement in information centric networks
20200374369 · 2020-11-26 ·

A content caching system enables an NDN network to place content closer to each end user(s) and to provide an explicit path for the target end user(s) to that content for better performance just in advance of users' anticipated request(s). The apparatus includes NDN routers and SDN controller employing a content commander, at least a content placement agent and at least one content analysis agent.

MANAGING NETWORK TRAFFIC FLOWS
20200374231 · 2020-11-26 ·

Technology related to managing network traffic flows is disclosed. In one example, a method can include searching a first data structure to determine whether a first entry associated with a network flow is present in the first data structure. In response to determining the first entry is present in the first data structure, at least a portion of the first entry can be used to generate an index for a flow cache. An action can be performed on the network packet as indicated by a flow cache entry, where the flow cache entry is located in the flow cache at the generated index.

Forwarding Entry Update Method and Apparatus
20200366626 · 2020-11-19 ·

A forwarding entry update method and apparatus, the method including receiving a write operation packet, where the write operation packet has write operation information, where the write operation information has write operation data and a write operation address, where the write operation data indicates a forwarding entry, and where the write operation address indicates an address to which the write operation data is to be written in a memory, obtaining the write operation information from the write operation packet, and writing the write operation data into the memory according to the write operation address in the write operation information.

Lookup-table hardware search engine

A lookup-table type TL-TCAM hardware search engine includes a SL decoder, a TL-TCAM array, and the data stored in the TL-TCAM hardware search engine is obtained by performing lookup table operation in the corresponding TCAM hardware search engine, the SL decoder is used to decode the search word and send it to the TL-TCAM hardware search engine array, and the decoding is to convert a search word SL corresponding to data in a TCAM hardware search engine table into a search word LSL corresponding to TL-TCAM hardware search engine table data, the effect is that TCAM adds a decoder, cooperates with the decoder and by lookup table method converts the TCAM table data to a new circuit unit that can be adapted to the added search line.

NETWORK SYSTEM INCLUDING MATCH PROCESSING UNIT FOR TABLE-BASED ACTIONS
20200336425 · 2020-10-22 ·

Methods and devices for processing packets with reduced data stalls are provided. The method comprises: (a) receiving a packet comprising a header portion and a payload portion, wherein the header portion is used to generate a packet header vector; (b) producing a table result by performing packet match operations, wherein the table result is generated based at least in part on the packet header vector and data stored in a match table; (c) receiving, at a match processing unit, the table result and an address of a set of instructions associated with the match table; and (d) performing, by the match processing unit, one or more actions in response to the set of instructions until completion of the instructions, wherein the one or more actions comprise modifying the header portion, updating memory based data structure or initiating an event.

INSTRUCTION PROCESSING METHOD AND CHIP
20200334040 · 2020-10-22 ·

This application provides an instruction processing method and a chip. The method includes sending, by the thread unit, a search instruction to the search engine unit. The search instruction includes a data address and a first search field, and the thread unit switches from a RUN state to a WAIT state. The method also includes receiving, by the thread unit, data and a program counter that are sent by the search engine unit. The thread unit switches from the WAIT state to the RUN state.

SYSTEMS AND METHODS FOR AUTOMATIC TRAFFIC RECOVERY AFTER VRRP VMAC INSTALLATION FAILURES IN A LAG FABRIC

Presented herein are systems and methods that provide traffic recover when virtual router redundancy protocol (VRRP) virtual media access control (VMAC) failures occur in a link aggregation group fabric environment. In one or more embodiments, automatic traffic recovery may be accomplished using internode link control messages to synchronize a VRPP VMAC failure that has been encountered by one LAG node with a LAG peer node. If a database associated with the failed LAG node comprises no entry that indicates that the failure scenario has previously occurred in the LAG peer node, a forwarding path entry rule may be generated to route traffic via the internode link, thereby, reducing data loss through routing failures and the like.