A network system includes a plurality of sub-network planes and global switches. The sub-network planes have a same network topology as each other. Each of the sub-network planes includes edge switches. Each of the edge switches has N ports. Each of the global switches is configured to connect a group of edge switches at a same location in the sub-network planes. In each of the sub-network planes, some of the N ports of each of the edge switches are connected to end nodes, and others of the N ports are connected to other edge switches in the same sub-network plane, other of the N ports are connected to at least one of the global switches.

A network device includes shelf controllers and interface unit controllers. An interface unit controller, of the interface unit controllers, is configured to receive a message from a different network device; determine whether a session exists for the message; identify a shelf controller, of the shelf controllers, based on the session when the session exists for the message; select the shelf controller, to receive the message, based on a load or mapping of the shelf controller when the session does not exist for the message; and transmit the message to the shelf controller. The shelf controller is configured to program a connection via a data plane of the network device.

An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD. For a packet PKT divided into subpackets, a subpacket of the packet PKT at the logic unit LA, and the packet specifying a target either: (A) the logic unit LC sends a subpacket of the packet PKT to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD; (B) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA sends a subpacket of the packet PKT to the logic unit LD; or (C) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD.

A packet processing apparatus has an ingress packet processing circuit, an egress packet processing circuit, and a traffic manager. The ingress packet processing circuit processes ingress packets received from ingress ports. The egress packet processing circuit processes egress packets to be forwarded through egress ports. The traffic manager deals with at least packet queuing and scheduling. At least one of the ingress packet processing circuit and the egress packet processing circuit includes a first packet processing unit located at a first packet flow path, and a second packet processing unit located at a second packet flow path. The first packet flow path is parallel with the second packet flow path, and programmability of the first packet processing unit is higher than programmability of the second packet processing unit.

Communication network systems are disclosed. In one or more implementations, the communication network system includes a plurality of network devices. Each of the plurality of network devices incorporates one or more multi-port switches, where each multi-port switch includes a connection to the network device incorporating the multi-port switch and a connection to at least one other port of another multi-port switch incorporated by another respective one of the plurality of network devices.

A RF router for routing n input signals to m destinations, where the router comprises a backplane coupled to a plurality of RF input terminals, a plurality of RF output terminals, a plurality of splitters and a plurality of connectors. The backplane is also coupled to a controller and a plurality of connectors for receiving a plurality of switching matrices. The RF router comprises a plurality of uv input switch matrices, a plurality of pq intermediate switch matrices and a plurality of rs output switch matrices, where at least one of the plurality of uv input switch matrices, the plurality of pq intermediate switch matrices and the plurality of rs output switch matrices are redundant.

An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD. For a packet PKT divided into subpackets, a subpacket of the packet PKT at the logic unit LA, and the packet specifying a target either: (A) the logic unit LC sends a subpacket of the packet PKT to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD; (B) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA sends a subpacket of the packet PKT to the logic unit LD; or (C) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD.

A switching device in a network system for transferring data includes one or more source line cards, one or more destination line cards and a switching fabric coupled to the source line cards and the destination line cards to enable data communication between any source line card and destination line card. Each source line card includes a request generator to generate a request signal to be transmitted in order to obtain an authorization to transmit data. Each destination line card includes a grant generator to generate and send back a grant signal to the source line card in response to the request signal received at the destination line card to authorize the source line card to transmit a data cell to the destination line card.

A method and apparatus for routing received connection demands through a photonic switch having multiple parallel instances of a switching plane is provided. Routing respects the constraint that each cell of the switch accommodates a maximum of one lightpath. Connection demands are routed one at a time via switching plane instances where it is possible without violating the constraint. When a demand cannot be routed, a re-arrangement step is performed. A previously routed demand that conflicts with the blocked demand is identified and de-allocated. The blocked demand is then routed in place of this de-allocated demand, which is now considered blocked. The process repeats until no blocked demands remain. Attempts to route additional demands of lower priority can also be made by checking whether each lower priority demand can be routed given the configuration of the switch to route existing demands.

A packet communication apparatus is configured to relay packets transmitted and received between information processing apparatuses. The packet communication apparatus includes: a network interface connectable to a network; a CPU to be a destination of at least one of a plurality of packets to be received through the network interface; a first buffer configured to hold the packets destined to the CPU in order to output the packets to the CPU; a second buffer having a plurality of planes and configured to hold copies of the packets destined to the CPU held in the first buffer in one of the plurality of planes; and a reception history controller configured to store a copy of a packet to a specified plane of the second buffer or to save copies of packets held in the second buffer to another storage area based on usage of the first buffer.