A packet communication apparatus is configured to relay packets transmitted and received between information processing apparatuses. The packet communication apparatus includes: a network interface connectable to a network; a CPU to be a destination of at least one of a plurality of packets to be received through the network interface; a first buffer configured to hold the packets destined to the CPU in order to output the packets to the CPU; a second buffer having a plurality of planes and configured to hold copies of the packets destined to the CPU held in the first buffer in one of the plurality of planes; and a reception history controller configured to store a copy of a packet to a specified plane of the second buffer or to save copies of packets held in the second buffer to another storage area based on usage of the first buffer.

In some examples, a switching system includes a plurality of fabric endpoints and a multi-stage switching fabric. A fabric endpoint of the system is configured to receive, via the switch fabric, a plurality of cell streams, wherein each cell of a cell stream of the plurality of cell stream is associated with a sequence number that defines a correct ordering of cells of the cell stream; assign subsequences of each cell stream of the plurality of cell streams to respective reorder engines of the fabric endpoint; concurrently reorder the assigned respective subsequences to produce respective ordered subsequences for the subsequences, wherein the ordered subsequences are ordered according to the correct ordering of the corresponding cell stream; interleave the respective ordered subsequences for each cell stream to produce reordered cell streams each having correctly ordered cells; and process each reordered cell stream according to the corresponding correct ordering of cells.

In some embodiments, an apparatus comprises a schedule module within a switch fabric system. At a first time, the schedule module is configured to access a list of status indicators associated with a group of egress port indicators. The list of status indicators includes a set of status indicators each of which has a value greater than a threshold. The schedule module is configured to randomly select a status indicator from the set of status indicators and configured to reduce the value of the selected status indicator. The schedule module is then configured to send the egress port indicator associated with the selected status indicator such that a data cell is sent from an egress port associated with that egress port indicator. At a second time, when the value of every status indicator from the list of status indicators is not greater than the threshold, the schedule module is configured to increase the value of every status indicator above the threshold.

A network system for a data center is described in which a switch fabric provides full mesh interconnectivity such that any servers may communicate packet data to any other of the servers using any of a number of parallel data paths. Moreover, according to the techniques described herein, edge-positioned access nodes, optical permutation devices and core switches of the switch fabric may be configured and arranged in a way such that the parallel data paths provide single L2/L3 hop, full mesh interconnections between any pairwise combination of the access nodes, even in massive data centers having tens of thousands of servers. The plurality of optical permutation devices permute communications across the optical ports based on wavelength so as to provide full-mesh optical connectivity between edge-facing ports and core-facing ports without optical interference.

A network switch includes circuitry and multiple ports, including multiple input ports and at least one output port, configured to connect to a communication network. The circuitry includes multiple distinct-flow counters, which are each associated with a respective input port and with the output port, and which are configured to estimate respective distinct-flow counts of distinct data flows received via the respective input ports and destined to the output port. The circuitry is configured to store packets that are destined to the output port and were received via the multiple input ports in multiple queues, to determine a transmission schedule for the packets stored in the queues, based on the estimated distinct-flow counts, and to transmit the packets via the output port in accordance with the determined transmission schedule.

A multi-node computing system. In some embodiments, the system includes: a first compute board, a second compute board, a plurality of compute elements, a plurality of memories, a first network plane connecting the first compute board and the second compute board, and a second network plane connecting the first compute board and the second compute board. The plurality of memories may store instructions that, when executed by the plurality of compute elements, cause the plurality of compute elements to: determine that a criterion for deactivating the first network plane is met, and deactivate the first network plane.

An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD. For a packet PKT divided into subpackets, a subpacket of the packet PKT at the logic unit LA, and the packet specifying a target either: (A) the logic unit LC sends a subpacket of the packet. PKT to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD; (B) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA sends a subpacket of the packet PKT to the logic unit LD; or (C) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD.

A switching device in a network system for transferring data includes one or more source line cards, one or more destination line cards and a switching fabric coupled to the source line cards and the destination line cards to enable data communication between any source line card and destination line card. Each source line card includes a request generator to generate a request signal to be transmitted in order to obtain an authorization to transmit data. Each destination line card includes a grant generator to generate and send back a grant signal to the source line card in response to the request signal received at the destination line card to authorize the source line card to transmit a data cell to the destination line card.

A packet forwarding method and a related apparatus to improve packet forwarding efficiency, where the method includes generating, by a controller, addressing information for a switching node, recording, by the controller, a correspondence between the switching node and the addressing information, and sending, by the controller, the addressing information to the switching node, so that the switching node forwards a packet according to the addressing information.

A system and method of transferring cells through a switch fabric having a shared memory crossbar switch, a plurality of cell receive blocks and a plurality of cell transmit blocks. The system determines, based on a number of cells queued up in respective output buffers in the cell transmit blocks, output buffers in the cell transmit blocks that can receive cells on a low latency path. The cells transferred include first cells that can be transferred on the low latency path and second cells that cannot be transferred via the low latency path. The first cells are transferred via a bypass mechanism in shared memory to the output buffers. The second cells are transferred by writing the second cells to shared memory, reading the second cells from shared memory and transferring the second cells read from shared memory to the output buffers in the cell transmit blocks.