Some embodiments provide a method for processing a packet for a pipeline of a hardware switch. The pipeline, in some embodiments, includes several different stages that match against packet header fields and modify packet header fields. The method receives a packet that includes a set of packet headers. The method then populates, for each packet header in the set of packet headers, (i) a first set of registers with packet header field values of the packet header that are used in the pipeline, and (ii) a second set of registers with packet header field values of the packet header that are not used in the pipeline.

Some embodiments provide a method for processing a packet for a pipeline of a hardware switch. The pipeline, in some embodiments, includes several different stages that match against packet header fields and modify packet header fields. The method receives a packet that includes a set of packet headers. The method then populates, for each packet header in the set of packet headers, (i) a first set of registers with packet header field values of the packet header that are used in the pipeline, and (ii) a second set of registers with packet header field values of the packet header that are not used in the pipeline.

A communication network comprises a central processing unit, data ingress ports and data egress ports configured to exchange data with a further network device of the communication network, and a plurality of co-processors that comprises frame normalization co-processors, ingress queuing co-processors, filtering and policing co-processors, intermediate queuing co-processors, a gatewaying co-processor, egress queuing co-processors, and a traffic shaping co-processor. The central processing unit configures and controls the data ingress ports, the data egress ports, and the plurality of co-processors to implement data processing paths in parallel or in a pipeline between the ingress ports and the egress ports.

A communication network comprises a central processing unit, data ingress ports and data egress ports configured to exchange data with a further network device of the communication network, and a plurality of co-processors that comprises frame normalization co-processors, ingress queuing co-processors, filtering and policing co-processors, intermediate queuing co-processors, a gatewaying co-processor, egress queuing co-processors, and a traffic shaping co-processor. The central processing unit configures and controls the data ingress ports, the data egress ports, and the plurality of co-processors to implement data processing paths in parallel or in a pipeline between the ingress ports and the egress ports.

The present disclosure relates to systems and methods for communicating in an Ethernet-based network using a transport layer without assistance of software-controlled mechanisms. In some embodiments, a first node includes a hardware link timer configured to determine packets transmitted under the transport layer hardware only Ethernet protocol to replay. The hardware link timer can include a first-in-first-out (FIFO) memory configured to store timing and status information associated with one or more links established by the first node. The hardware link timer can further include a timer associated with the one or more links that ticks according to a time period.