H04L49/254

USE OF STASHING BUFFERS TO IMPROVE THE EFFICIENCY OF CROSSBAR SWITCHES

A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.

Interconnection Network With Adaptable Router Lines For Chiplet-Based Manycore Architecture
20210344618 · 2021-11-04 ·

An interconnection network for a processing unit having an array of cores. The interconnection network includes routers and adaptable links that selectively connect routers in the interconnection network. For example, each router may be electrically connected to one or more of the adaptable links via one or more multiplexers and a link controller may control the multiplexers to selectively connect routers via the adaptable links. In another example, adaptable links may be formed as part of an interposer and the link controller selectively connect routers via the adaptable links in the interposer using interposer switches. The adaptable links enable the interconnection network to be dynamically partitioned. Each of those partitions may be dynamically reconfigured to form a topology.

CHASSIS CONTROLLER
20230289321 · 2023-09-14 ·

A non-transitory machine readable medium storing a program that configures managed forwarding elements to establish tunnels between the managed forwarding elements is described. From a particular managed forwarding element, the program receives information regarding coupling of a network element to the first managed forwarding element. Upon receiving the information, the program generates a set of universal flow entries for configuring another managed forwarding element to establish a tunnel to the particular managed forwarding element.

METHOD OF OPERATING A NETWORK
20230291695 · 2023-09-14 ·

A method is proposed for operating a network with several subscribers in the network. For this purpose, the network has at least one switch (10, 11, 12), at least two terminals and at least one controller. According to the invention, the controller can now communicate with one of the terminals via an application protocol. For this purpose, data is sent and/or received as data packets. In order to be able to schedule the communication, time slots are provided for sending the data packets that are adapted to a maximum possible packet size. For this purpose, the time slots have a start time and an end time so that they can overlap in different branches of the network. To optimize communication time, the packet sizes (5) can be changed. To avoid wasting bandwidth in the network, the time slots are adapted to the packet size accordingly by changing the start times and the end times (6).

Transmitting device, receiving device, packet transfer system,packet transfer method, and packet transfer program

A transmission device (10) includes a flow table (11) that stores identification information about an uninterruptible target flow; a transmission-side identification unit (12) that identifies whether a received packet is from the target flow or a non-target flow based on whether the received packet matches the identification information about the target flow stored in the flow table (11); a tag application unit (13) that applies, to packets from the target flow, an uninterruptible identifier indicating that the packets are from the target flow and a sequence number for distinguishing the packets from other packets; and a branch unit (14) that branches the packets from the target flow processed by the tag application unit (13) into packets to be transferred to an active path (41) among redundant routes and packets to be transferred to a backup path (42) among the redundant routes.

Packet storage based on packet properties

In some examples, a system on chip (SOC) comprises a network switch configured to receive a packet and to identify a flow identifier (ID) corresponding to a header of the packet. The SOC comprises a direct memory access (DMA) controller coupled to the network switch, where the DMA controller is configured to divide the packet into first and second fragments based on the flow ID and to assign a first hardware queue to the first fragment and a second hardware queue to the second fragment, and wherein the DMA controller is further configured to assign memory regions to the first and second fragments based on the first and second hardware queues. The SOC comprises a snoopy cache configured to store the first fragment to the snoopy cache or to memory based on a first cache allocation command, where the first cache allocation command is based on the memory region assigned to the first fragment, where the snoopy cache is further configured to store the second fragment to the snoopy cache or to memory based on a second cache allocation command, and where the second cache allocation command is based on the memory region assigned to the second fragment.

CONVERGED AVIONICS DATA NETWORK
20230283560 · 2023-09-07 ·

An avionics data network includes a network switch core configured for a time-sensitive networking (TSN) schema, a first and second set of networking end nodes communicatively coupled with the network switch core. The first set of networking end nodes includes a first subset of networking end nodes configured for a TSN schema and second subset of networking end nodes configured for a legacy Ethernet schema. The network switch core is configured to receive, from the first set of networking end nodes, a set of data frames, determine the respective schema of the set of data frames, forward the set of data frames to a predetermined queue on an egress port based on the determined respective schema, and transmit set of data frames to an end node having a corresponding schema.

Filter, port-capacity and bandwidth-capacity based circuits for load-balanced fine-grained adaptive routing in high-performance system interconnect
11757780 · 2023-09-12 · ·

A switch is provided for routing packets in an interconnection network. The switch includes a plurality of egress ports to transmit packets. The switch also includes one or more ingress ports to receive packets. The switch also includes a port and bandwidth capacity circuit configured to obtain (i) port capacity for a plurality of egress ports of the switch, and (ii) bandwidth capacity for transmitting packets to a destination. The switch also includes a network capacity circuit configured to compute network capacity, for transmitting packets to the destination, via the plurality of egress ports, based on a function of the port capacity and the bandwidth capacity. The switch also includes a routing circuit configured to route one or more packets received via one or more ingress ports of the switch, to the destination, via the plurality of egress ports, based on the network capacity.

Filter, Port-Capacity and Bandwidth-Capacity Based Circuits for Load-Balanced Fine-Grained Adaptive Routing in High-Performance System Interconnect
20230130276 · 2023-04-27 · ·

A switch is provided for routing packets in an interconnection network. The switch includes a plurality of egress ports to transmit packets. The switch also includes one or more ingress ports to receive packets. The switch also includes a port and bandwidth capacity circuit configured to obtain (i) port capacity for a plurality of egress ports of the switch, and (ii) bandwidth capacity for transmitting packets to a destination. The switch also includes a network capacity circuit configured to compute network capacity, for transmitting packets to the destination, via the plurality of egress ports, based on a function of the port capacity and the bandwidth capacity. The switch also includes a routing circuit configured to route one or more packets received via one or more ingress ports of the switch, to the destination, via the plurality of egress ports, based on the network capacity.

DIS-AGGREGATED SWITCHING AND PROTOCOL CONFIGURABLE INPUT/OUTPUT MODULE
20230137940 · 2023-05-04 ·

An input/output module (IOM) for use within a network storage system mounted within a rack enclosure. The IOM includes a switching component configured to provide top-of-rack (TOR) switching for data to be routed from input connectors to data storage devices within the rack enclosure. The IOM also includes a protocol interface configured to convert a protocol of the data from an input data protocol (e.g., Ethernet, Fibre Channel or InfiniBand™) to a protocol for use with the storage devices (e.g., nonvolatile memory express (NVMe) and Peripheral Component Interconnect Express (PCIe)). Among other features, the IOM allows switching to be dis-aggregated from a TOR switch and distributed throughout the data network of the rack.